STA problem: Maximum frequency of operation of a timing path

Problem: Figure 1 below shows a timing path from a positive edge-triggered register to a positive edge-triggered register. Can you figure out the maximum frequency of operation for this path?

Figure 1: A sample timing path

Solution:

The above timing path is a single cycle timing path. The maximum frequency is governed by setup timing equation. In other words, maximum frequency of operation is the maximum frequency (minimum time period of clock) that satisfies the following condition:

 T_ck->q + T_prop + T_setup - T_skew < T_period

Here,

 T_ck->q = 2 ns, T_prop = 4 ns, T_setup = 1 ns, T_skew = 1 ns, T_period 

Now,

T_period > 2 ns + 4 ns + 1 ns - 1 ns

T_period > 6 ns

So, the minimum time period of the clock required is 6 ns. And the maximum frequency that the above circuit can work is (1000/6) MHz = 166.67 MHz.

It should be noted that at if we operate this timing path at maximum frequency calculated, setup slack will be zero. :-)

In this post, we talked about frequency of operation of single cycle timing paths. Can you figure out maximum frequency of operation for half cycle timing paths? Also, there is a relation of maximum operating frequency to hold timing? Can you think about this situation?

Also read:

• Setup time and hold time basics
• Timing arcs
• What is Static Timing Analysis