So continuing on the previous post of two current sources in series, this example is important when you analyze lot of circuits.
Lets assume you simulate with ideal current sources
Case 1 : When top current source > lower current source
Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between increases.
The reason it increases is that top current source pumps in current but the down source only sinks lesser current, hence forth the rest of the current will charge up the cap at the node and hence forth increases the node potential.
Case 2 : When top current source < lower current source
Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between decreases.
The reason it increases is that top current source pumps in lesser current but the down source only sinks higher current, hence forth the rest of the current will be provided by the cap at the node and hence forth decreases the node potential.
Interested studentts should find time in simulating the circuit by replacing the current sources with NMOS and PMOS and understand what will happen.
This is an important step in understanding CMFB.
Lets assume you simulate with ideal current sources
Case 1 : When top current source > lower current source
Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between increases.
The reason it increases is that top current source pumps in current but the down source only sinks lesser current, hence forth the rest of the current will charge up the cap at the node and hence forth increases the node potential.
Case 2 : When top current source < lower current source
Since, they are ideal current sources, it happens that they will sink or source that much current ir respective of the voltage across the sources, so it implies that currents may be unequal in single wire and the node potential in between decreases.
The reason it increases is that top current source pumps in lesser current but the down source only sinks higher current, hence forth the rest of the current will be provided by the cap at the node and hence forth decreases the node potential.
Interested studentts should find time in simulating the circuit by replacing the current sources with NMOS and PMOS and understand what will happen.
This is an important step in understanding CMFB.
Neeraj,As for as i know, we should not connect two current sources in series because it is a KCL violation.Then, how come it possible to connect them in series. Please clarify.
ReplyDeleteHi Praveen, it is good to see you thought of it. Let me clarify you. First of all, no one is going to stop you from doing it atleast with ideal sources.
Delete1. When you have the circuit with ideal sources of cadence schematic, then you can have two different currents flowing.
2. If one of the current sources is replaced with NMOS/PMOS, then the current decided by the ideal current source is only going to still flow.
Let me explain in this way. When you have a current being pumped onto a node and some current being drawn out of a node, unless they are equal, there is no way that potential is going to zero. If both are ideal and if top > down, means u are pumping in more charge and drawing out less charge, which means that the KCL is getting violated. So the extra current flows into the node cap and the voltage increases.
Now I guess you can understand it better.
Any doubts, feel free to comment. Thanks for your interest. All the best