STA problem: Finding setup and hold slack considering ideal clock

Problem: Figure 1 below shows a timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop. Considering ideal clocks, and clock frequency of 100 MHz, find the setup and hold slacks for this timing path.

Solution:

Figure 1: Timing path

Ideally, all the flip-flops in design should get clock at the same time. So, ideal clock means that launch as well as capture flip-flops get clock at zero time. In other words, we can assume that clock skew is zero between start and end points.

As the clock frequency is given as a 100 MHz, time period = 1/frequency = 10 ns.

Let us first calculate the setup slack. The setup timing equation is given as:

T_ck->q + T_prop + T_setup - Tskew < T_period

And equation for setup slack is given as:

SS = T_{period -} (T_ck->q + T_prop + T_setup - Tskew₎  

Here,

T_ck->q = 2ns, T_prop (max value of delay of combinational logic) = 4 ns+ T_setup = 1 ns,   T_period = 10 ns

 Putting these values into equation for setup slack, we get setup slack for this timing path.

SS = 10 - (2 + 4 + 1 - 0) ns

SS = 3 ns

Now, hold slack can be found out from the hold timing equation. The hold timing equation is given as:

T_ck->q  + T_prop > T_hold + T_skew

Here,

T_ck->q  =  2 ns, T_prop (min value of combinational propagation delay) = 4 ns, T_hold = 1 ns

 And the equation for hold slack is given as:

HS = T_ck->q  + T_prop  - (T_hold + T_skew) 

HS = 2 + 4 - (1 + 0) = 5 ns 

So, for this timing path, setup slack value is 3 ns and hold slack value is 5 ns.