Clock gating checks

Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. And a number of control signals are there which control these clocks. These signals are behind switching on and off the design. Let us say, we have a simple design as shown in the figure below. Pin ‘SEL’ selects between two clocks. Also, ‘EN’ selects if clock will be propagating to the sub-design or not. Similarly, there are signals that decide what, when, where and how for propagation of clocks. Some of these controlling signals may be static while some of these might be dynamic. Even with all this, these signals should not play with waveform of the clock; i.e. these should not cause any glitch in clock path. There are both architectural as well as timing care-abouts that are to be taken care of while designing for signals toggling in clock paths. This scenario is widely known as ‘clock gating’. The timing checks that need to be modeled in timing constraints are known as ‘clock gating checks’.

Figure 1: A simplest clocking structure

Definition of clock gating check: A clock gating check is a constraint, either applied or inferred automatically by tool, that ensures that the clock will propagate without any glitch through the gate.

Types of clock gating checks: Fundamentally, all clock gating checks can be categorized into two types:

AND type clock gating check: Let us say we have a 2-input AND gate in which one of the inputs has a clock and the other input has a data which will toggle while the clock is still on.

Figure 2: AND type clock gating check; EN signal
controlling CLK_IN through AND gate

Since, the clock is free-running, we have to ensure that the change of state of enable signal does not cause the output of the AND gate to toggle. This is only possible if the enable input toggles when clock is at ‘0’ state. As is shown in figure 3 below, if ‘EN’ toggles when ‘CLK_IN’ is high, the clock pulse gets clipped. In other words, we do not get full duty cycle of the clock. Thus, this is a functional architectural miss causing glitch in clock path. As is evident in figure 4, if ‘EN’ changes during ‘CLK_IN’ are low, there is no change in clock duty cycle. Hence, this is the right way to gate a clock signal with an enable signal; i.e. make the enable toggle only when clock is low.

Figure 3: Clock being clipped when ‘EN’ changes when ‘CLK_IN’ is high

Figure 4: Clock waveform not being altered when ‘EN’ changes when ‘CLK_IN’ is low

Theoretically, ‘EN’ can launch from either positive edge-triggered or negative edge-triggered flops. In case ‘EN’ is launched by a positive edge-triggered flop, the setup and hold checks will be as shown in figure 5. As shown, setup check in this case is on the next positive edge and hold check is on next negative edge. However, the ratio of maximum and minimum delays of cells in extreme operating conditions may be as high as 3. So, architecturally, this situation is not possible to guarantee the clock to pass under all conditions.

Figure 5: Clock gating setup and hold checks on AND gate when 'EN' launches from a positive edge-triggered flip-flop

On the contrary, if ‘EN’ launches from a negative edge-triggered flip-flop, setup check are formed with respect to the next rising edge and hold check is on the same falling edge (zero-cycle) as that of the launch edge. The same is shown in figure 6. Since, in this case, hold check is 0 cycle, both the checks are possible to be met for all operating conditions; hence, this solution will guarantee the clock to pass under all operating condition provided the setup check is met for worst case condition. The inactive clock state, as evident, in this case, is '0'.

Figure 6: Clock gating setup and hold checks on AND gate when ‘EN’ launches from negative edge-triggered flip-flop

Figure 7: An OR gate controlling a clock signal 'CLK_IN'

OR type clock gating check: Similarly, since the off-state of OR gate is 1, the enable for an OR type clock gating check can change only when the clock is at ‘1’ state. That is, we have to ensure that the change of state of enable signal does not cause the output of the OR gate to toggle. Figure 9 below shows if ‘EN’ toggles when ‘CLK_IN’ is high, there is no change in duty cycle. However, if ‘EN’ toggles when ‘CLK_IN’ is low (figure 8), the clock pulse gets clipped. Thus, ‘EN’ must be allowed to toggle only when ‘CLK_IN’ is high.

Figure 8: Clock being clipped when 'EN' changes when 'CLK_IN' is low

Figure 9: Clock waveform not being altered when 'EN' changes when 'CLK_IN' is low

As in case of AND gate, here also, ‘EN’ can launch from either positive or negative edge flops. In case ‘EN’ launches from negative edge-triggered flop, the setup and hold checks will be as shown in the figure 10. The setup check is on the next negative edge and hold check is on the next positive edge. As discussed earlier, it cannot guarantee the glitch less propagation of clock.

Figure 10: Clock gating setup and hold checks on OR gate when ‘EN’ launches from negative edge-triggered flip-flop

If ‘EN’ launches from a positive edge-triggered flip-flop, setup check is with respect to next falling edge and hold check is on the same rising edge as that of the launch edge. The same is shown in figure 11. Since, the hold check is 0 cycle, both setup and hold checks are guaranteed to be met under all operating conditions provided the path has been optimized to meet setup check for worst case condition. The inactive clock state, evidently, in this case, is '1'.

Figure 11: Clock gating setup and hold checks on OR gate when 'EN' launches from a positive edge-triggered flip-flop

We have, thus far, discussed two fundamental types of clock gating checks. There may be complex combinational cells other than 2-input AND or OR gates. However, for these cells, too, the checks we have to meet between the clock and enable pins will be of the above two types only. If the enable can change during low phase of the clock only, it is said to be AND type clock gating check and vice-versa.

SDC command for application of clock gating checks: In STA, clock gating checks can be applied with the help of SDC command set_clock_gating_check.

Also read:

• Clock gating interview questions

Need for clock gating checks - need for glitchless clock propagation

One of the most important things in designs is to ensure glitch free propagation of clocks. Even a single glitch in clock path can cause the chip to be metastable and even fail. A glitch is any unwanted clock pulse that may cause the sequential cells to consider it as an actual clock pulse. Thus, a glitch can put your device in an unwanted state that is functionally never possible. That is why; there should never be a glitch in clock path. Every effort should be done by designers to minimize its probability. The figure below shows a flip-flop receiving a data signal and a clock signal; if there is some glitch (unwanted change of state) in clock, it will take it as a real clock edge and latch the data to its output. However, if the pulse is too small, the data may not propagate properly to output and the flop may go metastable.

Figure showing functional glitch in clock path

There may be following kind of cells present in clock path:

     1)      Buffers/inverters: Since, there is only one input for a buffer/inverter, the glitch may occur on the output of these gates only through coupling with other signals in the vicinity. If we ensure that the buffer/inverter has good drive strength and that the load and transition at its output are under a certain limit, we can be certain that the glitch will not occur.

      2)   Combinational gates: There can be combinational gates other than buffers/inverters in clock path, say, a 2-input AND gate having an enable signal that tells if the clock is to be propagated or not. Each combinational gate might have one or more clocks and data/enable pins. Let us say, we have a two input AND gate with one input as clock and the other acting as an enable to the clock. We can have following cases possible:

i)             The other input is static: By static, we mean the other input will not change on the fly. In other words, whenever the enable will change, the clock will be off. So, enable will not cause the waveform at the output of the gate to change. This case is similar to a buffer/inverter as the other input will not cause the shape of the output pulse to change.

ii)                The other input is toggling: In this case, the enable might affect the waveform at the output of the gate to change. To ensure that there is not glitch causes by this, there are certain requirements related to skew between data and clock to be met, which will be discussed later in the text. These requirements are termed as clock gating checks.

3   3)    Sequential gates: There may also be sequential gates in clock path, say, a flop, a latch or an integrated clock gating cell with the clock at its clock input and the enable for the clock will be coming at its data input. The output of these cells will be a clock pulse. For these also, two cases are possible as in case 2. In other words, if the enable changes when clock is off, the enable is said to be static. In that case, the output either has clock or does not have clock. On the other hand, if the input is toggling while clock is there at the input, we may get away by meeting the setup and hold checks for the enable signal with respect to clock input.

As discussed above, to ensure a glitch free propagation of clock at the output of the combinational gates, we have to ensure some timing requirements between the enable signal and clock. These timing requirements ensure that there is no functionally unwanted pulse in clock path. If we ensure these timing requirements are met, there will be no functional glitch in clock path. However, glitches due to crosstalk between signals can still occur. There are other techniques to prevent glitches due to crosstalk. The functional glitches in clock path can be prevented by ensuring the above discussed timing requirements. In STA, these requirements are enforced on designs through timing checks known as clock gating checks. By ensuring these checks are applied and taken care of properly, an STA engineer can sign-off for functional glitches. In later posts, we will be dealing with these checks in more details.

Also read:

• All about clock signals
• Clock gating checks
• Clock gating checks at a MUX
• Setup time and hold time - static timing analysis
• Worst slew propagation