A latch is a digital logic circuit that can sample a 1-bit digital value and hold it depending upon the state of an enable signal. Based upon the state of enable, latches are categorized into positive level-sensitive and negative level-sensitive latches.
Positive level-sensitive latch: A positive level-sensitive latch follows the input data signal when enable is '1' and keeps its output when the data when it is '0'. Figure 1 below shows the symbol and the timing waveforms for a latch. As can be seen, whenever enable is '1', out follows the data input. And when enable in '0', out remains the same.
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| Figure 1(a): Positive level- Figure 1(b): Timing waveform for a positive level- sensitive latch sensitive latch |
Negative level-sensitive latch: A negative level-sensitive latch follows the input data when enable is '0' and keeps its output when input is '1'.
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| Figure 2(a): Negative level- Figure 2(b): Timing waveform for a negative level- sensitive latch sensitive latch |
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Latch timing arcs: Data can propagate to the output of the latch in two ways as discussed below:
- Out changes with Data: This happens when enable is in its asserted state (for example, for a positive level latch). When this happens, Out follows Data as there is a direct path between Data and Out when Enable is '1'. This scenario is depicted in figures 1(b) and 2(b) above wherein out is shown toggling when Data toggles. The latch is, thus, said to have a timing arc from Data to Out.
- Out changes with Enable: This happens when Data at input changes when Enable is in its de-asserted state. When this happens, latch waits for Enable to be asserted, then, follows the value of Data. As figure 3 shows, Data had become stable a lot earlier, but out toggled only when enable became asserted. So, in latches, there exists a timing arc from Enable to Out.
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| Figure 3:When data changes during enable is in de-asserted state, output waits for the enable to assert. Only then, the effect of input propagated to output |
- Relation between Data and Enable: If Data toggles very close to the closing edge of Enable, then, there might be a confusion as if its effect will be propagated to output or not (as discussed later in this post). To make things more deterministic, we impose a certain condition that Data should not toggle when Enable is getting de-asserted. This relationship can be modelled as setup and hold arcs. So, there are setup and hold timing arcs between data and enable pins of a latch. These will be discussed below in detail.
Setup time and hold time for a latch: The most commonly used latch circuit is that built using inverters and transmission gates. Figure 4 shows the transmission gate implementation of a positive level-sensitive latch. The Enable has been shown as CLK as usually is the case in sequential state machines. This circuit has two phases, as is expected for a latch:
- When CLK = '1', Transmission gate at the input gets ON and there is a direct path between Data and Out
- When CLK = '0', transmission gate in the loopback path gets ON. Out holds its value
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Figure 4: Positive level-sensitive latch using transmission gates
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Now, when CLK transitions from '1' to '0', it is important that Data does not toggle. The time before the clock falling edge that Data should remain stable is known as latch setup time. Similarly, the time after the clock falling edge that Data should remain stable is called latch hold time.
Let us go into the details of what latch setup and hold time should be for transmission gate latch. If we want the data to be propagated properly to the output, then Data should be stable for atleast some time before closing of the input transmission gate. This time is such that it goes into the memory of latch; i.e., before input transmission gate closes, Data should traverse both the inverters of the loop. So, setup time of the latch involves the delay of input transmission gate and the two inverters. Figure 5 below shows the setup time for the latch.
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| Figure 5: Setup time for latch |
Similarly, if we do not want the data to propagate to output, it must not cross input transmission gate so that it does not disturb the present state of the latch. This server as the hold time for the latch. Assuming CLK' takes one inverter delay, input transmission gate will close after one inverter delay only. So, the hold time for Data is one inverter delay minus transmission gate delay. Please refer to figure 6 below for the illustration of this. (CLK)' is formed from CLK after a delay equivalent to an inverter delay. Only then, input transmission gate will switch off. If we want the data not to propagate to Out, we have to ensure that it does not cross input transmission gate. So, Data should not be present at the transmission gate's input at time (T(inv) - T(tg)). In other words, it has to be held stable this much time after CLK edge. This is the hold time for the latch.
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| Figure 6: Hold time for latch |
Please note that there are other topologies also possible for latches such as dynamic latches etc. The setup time and hold time calculations for such topologies will vary, but the underlying principle will remain same, which is as follows:
- Setup time ensures that the data propagates to the output at the coming clock edge
- Hold time ensures that the data does not propagate to the output at the present/previous clock edge
Setup checks and hold checks for latches: As discussed above, the decision for the data to be latched or not to be latched is made at the closing edge. So, the setup and hold checks are with respect to latch closing edge only. However, since, latches are transparent during half of the clock period, we can assume as if the capturing edge is flexible and stretches all over the active level of the latch. This property enables a very beautiful concept known as "time borrowing" for latches.
