Why is body connected to ground for all nmos and not to VDD

To prevent latch-up in CMOS, the body-source and body-drain diodes should not be forward biased; i.e, body terminal should be at same or lesser voltage than source terminal (for an NMOS; for a PMOS, it should be at higher voltage than source). This condition will be satisfied if we connect all the nmos bodies to their respective sources. But we see that all the body terminals are connected to a common ground.

This is due to the reason that all the nmos transistors share a common substrate, and a substrate can only be biased to one voltage. Although it introduces body effect and makes transistors slower and deviate from ideal mos current equation, there is no other way.

One could achieve different body voltage for all nmos transistors by putting all transistors in different wells, but that would mean a tremendous penalty in terms of area as there needs to be minimum size and separation that needs to be maintained which is huge in comparison to transistor sizes. This is the reason why body is connected to ground for all NMOS.

Similarly, body of all PMOS transitors is connected to a common terminal VDD.

Transmission Gates

Transmission gates represent another class of logic circuits, which use Transmission gates as basic building block. A transmission gate consist of a PMOS and NMOS connected in parallel. Gate voltage applied to these gates is complementary of each other (C and Cbar shown in figure 1). Transmission gates act as bidirectional switch between two nodes A and B controlled by signal C. Gate of NMOS is connected to C and gate of PMOS is connected to Cbar(invert of C). When control signal C is high i.e. VDD, both transistor are on and provides a low resistance path between A and B. On the other hand, when C is low, both transistors are turned off and provide high impedance path between A and B.

Figure 1: Transmission gate

A detailed analysis of working of transmission gates follows:

When input node A is connected to VDD and control logic C is also high, C = 1 : The output node B may be connected to capacitor. Let us say, voltage at output node is Vout.

For PMOS, Source of is at higher voltage than drain.

For NMOS, drain is at higher voltage than Source terminal.

 Hence, node A will act as source terminal for pMOS and as drain terminal for nMOS.

Drain to Source and gate to source voltages for nMOS are as :

                                                       V_DS,n = VDD – Vout

                                                       V_GS,n = VDD – Vout

For nMOS to be turned off, V_GS,n < V_th,n
                                             VDD – Vout < V_th,n
                                             Vout > VDD – V_th,n (Cut off region)

For Vout < VDD – V_th,n

V_DS,n > V_GS,n – V_th,n

i.e. will operate in saturation mode

Similarly for pMOS,

V_DS,p = Vout - VDD
V_GS,p = – VDD

For pMOS to be turned off V_GS,p > v_th,p threshold voltage for pMOS is –ve so pMOS will always be turned on.

For pMOS to operate in linear region, V_DS > V_GS – v_th,p

Vout – VDD > -VDD – V_th,p

Vout > - V_th,p

Vout > |V_th,p|

For Vout ≤ |Vth,p|, pMOS will be in saturation mode.

Unlike nMOS, pMOS remain turned on regardless of output voltage Vout

Thus PMOS will always be turned on, and as we know that PMOS Passes a strong 1 so voltage level high will be transmitted unattenuated.

Similarly,

When voltage at node A,Vin = 0 and C = VDD, node A will act as source terminal for nMOS and will act as drain for pMOS. nMOS will always be turned on hence level 0 will also be transmitted unattenuated.

when voltage at node A,Vin = VDD and C = 0 node A will act as drain terminal for nMOS and source terminal for pMOS

V_GS,n = 0 – VDD < V_th,n (cut off region)

Hence nMOS will be turned off

VGS,p = VDD – VDD = 0 > V_th,p (Cut off region)

Thus both transistor will remain off. Path between A and B will be an open circuit.

when voltage at node A,Vin = 0 and C = 0 : node A will act as source terminal for nMOS and will act as drain for pMOS.

V_GS,n = 0 – 0 = 0 <V_th,n (Cut off region)

V_GS,p = VDD – Vout

V_GS,p will be some positive voltage and threshold voltage of pMOS ,Vth,p is negative.

V_GS,p > V_th,p (Cut off region)

Hence both transistor will remain off and high impedance path exists between A and B.

Also read:

• Regions of operation of MOS transistors
• Enhancement and depletion MOSFETs
• Depletion MOSFETs and negative logic : why it is not possible
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