As we know that cell delay is a function of output load capacitance. The most simplistic equivalent circuit of a logic gate driving an output can be assumed as given in figure 1:
The purpose of logic gate is to propagate the effect of logic value available at its input to the output. Based upon whether '0' or '1' is to be propagated to the output. The corresponding is achieved by charging and discharging of the output load capacitance. Propagating a logic '0' will mean discharging of the load capacitance, and vice-versa. Drive strength of the logic gate is the its relative capability to charge/discharge the capacitance present at its output. Now, the time constant, and hence, delay of the circuit is "RC".
So, for a cell with higher drive strength, corresponding "R" is lesser than the one with lower drive strength. So that for same load capacitance "C", delay is lower for a cell with higher drive strength as it can charge the capacitance in lesser time.
How drive strength varies with size of a cell: Let us talk in terms of MOSFETs, although this is valid in terms of every device in general. We know that for a given technology standard cell library, length of all transistors is kept constant. For instance, 90 nm technology will have gate length of all transistors as ~90 nm. And channel resistance of the MOSFET is inversely proportional to "W/L" of the transistor. So, a simple way to decrease channel resistance is to increase "W" of the transistor. So, a transistor with more area will have lesser resistance. Or we can say that a logic gate with bigger transistors will have more drive strength.
What is unit drive strength: In a standard cell library, we generally see cells labelled as "1X", "2X" and so on. But what is meant by the number that you see with drive strength? In general, the lowest size logic gate is labelled as unit drive strength. The drive strength numbers of other cells are laelled relative to unit drive strength cell.
Read next: How delay of a cell changes with drive strength
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Read next: How delay of a cell changes with drive strength
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Hello. I have some question. Generally, you said that drive strength increases when the cell size increases, but NORx0 and NORx1 in the saed 28/32 library have the same layout area. Why is the drive strength different in this case?
ReplyDeleteHi
DeleteI think this may be due to the area required for wires inside the standard cell. For a 1X cell vs 2X cell, the number of wires will be constant. The actual transistor area must be less for x0 cell. You can confirm this by looking at power numbers (power will be less for lesser transistor sizes) and the actual layout (or DEF) view of the standard cell.
Hi, Size of transistor increases means the W of active poly gate is increasing, that doesn't mean area/size of std cell will increase. If you check the GDS for x0 & x1 the OD (overlap over active poly) sizes will be different. for eg. for x0 if OD width is 0.1u , for X1 it will be doubled ~0.2u. Size of cell depends on DRC requirement. Hope this answers your question
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ReplyDeleteWe see something like 10x5 or 4x5 in the standard cell name, please let me know what does x5 mean ? what I understand 10x or 4x indicates drive strength.
Hi
DeleteThe nomenclature is highly dependent upon vendor, you can refer documentation for details.
Usually for eg. And3×2 means 3 input nand gate with 3 times drive strength.
Deletethat may be true, but there can be other things as well; which can be highly specific to the library. We cannot generalize this.
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