How delay of a standard cell changes with drive strength

A standard cell (let us say a buffer) can be represented as shown in figure 1 below, where 
R = Channel resistance 
Cds = Drain-to-source capacitance (internal capacitance of cell)
Cload = Load capacitance


So, RC time constant can be represented as "R * (Cds + Cload)".

What happens on increasing the drive strength? In our post "what is meant by drive strength", we discussed that the drive strength of a standard cell increases when we increase the size of its transistors. So, basically, a cell with drive strength 2X will have twice of width as compared to the one with 1X drive strength.
And we know that
Channel resistance decreases with "W".
Drain-to-source capacitance increases with "W".
So,  upon increasing the drive strength, its internal capacitance will increase and channel resistance will reduce by same amount. The same is depicted in figure 2 below.


Time constant of "1X" buffer = R * (Cds + Cload)
 Time constant of "2X" buffer = R/2 * (2Cds + Cload) 
Now, let us talk of following scenarios:

Special case 1: Load capacitance is negligible.
In this scenario, we are left with only internal resistance and capacitance of the cell.

Time constant of "1X" buffer = R * Cds
Time constant of "2X" buffer = R * Cds
So, in this case, there should not be any impact of increasing the drive strength of standard cell on delay. So, in case there is negligible load, we should not upsize the standard cell. Doing so may instead increase the overall path delay as increased drive strength cell will present increased load to the previous stage cell, thereby increasing the delay of previous stage.

Special case 2: Load capacitance is very large as compared to internal capacitance.
In this scenario,
Time constant of "1X" buffer = R * Cload
Time constant of "2X" buffer = (R * Cload ) / 2 
So, second buffer will take approximately half the time to charge the load capacitance as compared to "1X" buffer.

So, we see that the the maximum possible benefit in delay by increasing the drive strength of standard cell is a reduction by a factor of two. In the worst case, we may not see any benefit at all.

We can also look at above equation by splitting cell delay into two components:
  1. Cell delay due to its own intrinsic capacitance: It does not scale by drive strength and is a constant value for one kind of standard cells.
  2. Cell delay due to external load capacitance: It is variable and decreases as we increase the drive strength of standard cell.

12 comments:

  1. Remarkable! Its in fac awesome piece of writing, I have got
    much clear idea concerning from this post.

    ReplyDelete
  2. easy to understand and good points...nice

    ReplyDelete
  3. Assume explanation

    ReplyDelete
  4. thanks. i have one question..
    if i use the up size drive strength cell, i have the cons that is C load of previous stage cell and big size of chip. is that all about cons?

    in other words, is the reason why we use the unit drive strength cell(1x) that Cload and size?

    ReplyDelete
    Replies
    1. If you are thinking purely from timing perspective, then yes, this is the only cons. And this can, in fact, increase the delay of overall path as well.

      On the other hand, increasing the drive strength increases area and power both due to big size and large current flowing in bigger drive strength cell.

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  5. I have 2 questions.
    1) if the load is itself another inv, because i have 2 of them in series, the RC will be the same for both drive strengths, correct? if claod = cint I have: R(2Cint) for the first and R/2(4Cint) for the second.
    2) how can you modify this model if for example, other than Cload, there is the Resistance of the wire going from the output of the inv to Cload to be considered as well? I mean a series resistance between Cint and Cload. What would be the impact of two different drive strengths in this case?

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    Replies
    1. Hi

      1. Correct for this

      2. If there is a resistance as well, then it will become a lot complex. Then, it will have to be broken into 2 parts.
      a. cell delay -> which will be derived from "effective capacitance as seen at cell output node. This is how timing tools calculate cell delays
      b. Net delay -> This can be calculated with different net delay modes, example Elmore delay model

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  6. Hi, I have a question.
    What are the possible techniques that I can implement to practically balance the drive strength of the a path in my design

    ReplyDelete
    Replies
    1. Hi, you can refer to this post. I hope this helps.
      https://vlsiuniverse.blogspot.com/2017/02/fixing-setup-violations.html

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