Post your query

Hi Friends

Please feel free to post your queries as comments. We will try our level best to answer these. You can also write to us at myblogvlsiuniverse@gmail.com.

26 comments:

  1. Unknown11 March 2019 at 04:20

    I want to join rv vlsi college in banglore they suggested me 8books to attend the entrance test for vlsi with in one week.please help me how i have to prepare

    ReplyDelete
    Replies
    1. VLSI UNIVERSE11 March 2019 at 10:18

      Hi Prasanth

      In my opinion, you can prioritize in below order:

      1. MOSFET questions, MOSFET as a switch, MOSFET as an amplifier etc.

      2. Flip-flops and frequency divider circuits. FSM basics

      3. RC, RLC circuits solving

      4. Control systems

      5. Microprocessors

      Delete
  2. Unknown3 August 2019 at 08:22

    Can you please explain Hold time check for clock with Jitter?

    ReplyDelete
    Replies
    1. VLSI UNIVERSE4 August 2019 at 06:51

      Hi

      I suggest you to go through following.

      https://vlsiuniverse.blogspot.com/2017/08/can-jitter-in-clock-effect-setup-and.html

      Delete
  3. Unknown25 September 2019 at 18:57

    In this below link and in the case 3.What do you mean by design violation? Is that we shouldn't design the system by expecting synchronous data from the launch flop which is driven by same clock but with asynchronous reset. if so what is the alternative take to overcome this kind of handling.

    https://vlsiuniverse.blogspot.com/2019/06/asynchronous-reset-assertion-timing.html

    ReplyDelete
    Replies
    1. VLSI UNIVERSE25 September 2019 at 20:05

      Hi

      Your statement is valid only when the capturing flip-flop expects data when the launching flip-flop gets reset. We can do either of following in this case:

      1. The capturing flip-flop should also get into reset state whenever launch flip-flop gets into reset state (they should be driven by same reset synchronizer)

      2. There should be synchronization mechanism in place so that any probable metastability gets absorbed

      3. Reset should launch from a synchronous source as we explained in example in case 3

      Delete
    2. Unknown26 September 2019 at 09:46

      I had another query, as you mentioned earlier asynchronous reset need not to be timed? right. What, if all the flops of certain blocks is being driven to meta-stable state due to asynchronous reset application. It may not cause any functional issue. But the entire block ( Combinational/sequential) will be in meta-stable state for certain duration which will impact huge power drain or even cause combinational logic to burn (correct my understanding on meta-stability if i'm wrong.

      Delete
    3. VLSI UNIVERSE26 September 2019 at 10:30

      Hi

      Yes, asynchronous reset assertion does not need to be timed, provided it does not cause any metastability issue as you described. The post I have written is about this issue only. :-) I hope I was able to explain the scenarios well in thata post.

      Also, in addition to large power burn-down, functional issues are also caused by metastability.

      Delete
  4. Unknown25 September 2019 at 18:59

    Hi,

    What is glitch in the clock? How does it effects the system and how it arrives.Whether glitch means meta-stable region of clock ?

    ReplyDelete
    Replies
    1. VLSI UNIVERSE25 September 2019 at 20:12

      Hi

      You can go through below link. I hope it helps.

      https://vlsiuniverse.blogspot.com/2014/04/glitch-free.html

      Delete
  5. Unknown25 September 2019 at 19:00

    Hi,
    What is Feedback MUX in the design?

    ReplyDelete
    Replies
    1. VLSI UNIVERSE25 September 2019 at 20:07

      Hi

      Can you elaborate more on this? Are you talking about "feedback mux" error in VHDL?

      Delete
    2. Unknown26 September 2019 at 09:48

      yes, why the flop which is not being resetted is throwing such error. what is relationship between the term Feed back mux and flop which is not being made as zero

      Delete
    3. VLSI UNIVERSE26 September 2019 at 10:28

      Hi

      I am not able to think of why it can happen. Can you post your code here.

      Delete
  6. Unknown30 September 2019 at 07:03

    Hi ,

    Kindly explain the concept of blocking and non-blocking assignment in verilog. If any post is already available please let me know.

    ReplyDelete
    Replies
    1. VLSI UNIVERSE1 October 2019 at 22:43

      Hi

      I have found one of the links that may be of help to you.

      http://www.asic-world.com/tidbits/blocking.html

      Delete
  7. Unknown8 October 2019 at 10:00

    Hi,
    whether there is any possibility to use the hold violation of the chip after it is being manufactured ( Post silicon).
    we can fix setup by reducing frequency of operation. similarly for hold issue increasing voltage of operation will it helps?

    ReplyDelete
  8. VLSI UNIVERSE21 October 2019 at 01:00

    Hi

    There are two categories of hold checks:

    1. Zero cycle hold check: Most of the cases comprise of zero cycle hold check. In this case, if there is a hold violation, slowing the frequency will not help.

    2. Non-zero cycle hold checks: Here, reducing the frequency helps in hold slack recovery as in setup checks. Hence, in this case, you can use the chip after reducing frequency.

    ReplyDelete
  9. Anonymous29 October 2019 at 13:08

    Hi, I had interview and there were two hard questions
    1. In advanced technologies, why do we need multiple masks for the same layers?
    2. Clock gating oositions in the path, how this affect the coverage and what is the effect of that in timing?

    Thanks

    ReplyDelete
    Replies
    1. VLSI UNIVERSE30 October 2019 at 08:45

      Hi

      This is because for some of the layers, minimum geometry width is very smaller as compared to the wavelength of light used so that there is a possibility of merging of the two lines drawn. Thus, to make it possible for the light to differentiate between two lines, different masks are used.

      Delete
  10. Anonymous4 December 2019 at 07:20

    how can we construct a 101 non overlapping counter using only combinational circuit for 32 bit input
    for example on considering 10101001 i want an output as 1 since there is only 1 101 non overlapping sequence

    ReplyDelete
    Replies
    1. VLSI UNIVERSE20 March 2020 at 20:58

      Hi

      I have tried to answer your query at https://vlsiuniverse.blogspot.com/2020/03/design-query-how-can-we-construct-101.html

      Delete
  11. Unknown4 January 2020 at 19:32

    Explain the Glitch free special mux working (switching between scan clock and capture clock)

    ReplyDelete
    Replies
    1. VLSI UNIVERSE21 March 2020 at 19:13

      Hi

      You can go through below link. Please feel free to discuss in case of any queries.
      https://vlsiuniverse.blogspot.com/2017/03/clock-multiplexer.html

      Or

      https://www.eetimes.com/techniques-to-make-clock-switching-glitch-free/#

      Delete
  12. Arunkumar.N12 January 2020 at 22:14

    what is the command to find out no.of glitches present in the design

    ReplyDelete
    Replies
    1. VLSI UNIVERSE21 March 2020 at 19:32

      I am sorry this question is very generic and I dont think I will be able to help you on this question. Sorry again for not being able to help.

      Delete

Thanks for your valuable inputs/feedbacks. :-)

Subscribe to: Post Comments (Atom)