IIT Delhi - Par1 - Interview Experiences

Before going to Delhi, just 2 days back I got Kharagpur VLSI, so I was a bit uncertain whether I will be going because I was comfortable with VLSI in top 5 IITs. But then to my luck, the reservation was confirmed and I along with 2 others have gone there. From Hyderabad, it almost took 30 hours journey.

I had a lot of Interviews in IIT Delhi – IEC, VDTT, JTM, Computer Technology.

We got into the college 1 day before the Interview. IIT Delhi is good in one aspect that it doesn’t have written tests. I have not been qualifying the tests so far may be because they were written test  ( Jokes are excuses some times)

I have a friend Roopesh Sharma there ( JTM Student and AIR 245 in Gate 2014) . The hostels in IIT Delhi are not that great in terms of look. Food is ok. My friend had luckily made me familiar with few seniors of IEC and VDTT.

I had conversation with few persons of both IEC, VDTT. I came to know about the process but then I had to appear for the process.

VDTT Interview : 

                            Initially they verified our documents and divided us into few groups and each group for each Interview panel. Mine was Panel 2. Initially every panel students were coming out but in our panel there was no one who even went inside. I was the first person as per sequence in my panel.

After a while, I was asked to come into. The Panel had 2 Professors, old enough to make me afraid. I greeted them and even they followed it up with a nice little smile, that made me feel a bit relaxed.

I was asked the following questions.

                                    1. Draw CMOS Inverter

                                    2. In the same diagram, now ground and power supply are exchanged?

                                     3. Implement Y = AB+C+D (whole bar) in NMOS,PMOS,CMOS logics

                                       4. If I add 2 sin signals with one of them having frequency f1 and other 2*f1                                               or say some 1000*f1. Then draw the resultant as a diagram.

                                            5. Why CMOS. Why not NMOS or PMOS.

The results where supposed to be announced in the evening. 

               I was waiting upto evening.

I was in an unknown status. Going by my heart, I thought I was in. But then Bangalore and Madras kept me thinking and reminding about my luck again and again...

JTM Interview :

                            Didn't attend the Interview because some how I was confident about VDTT and also even if I don't do VDTT well, I had IEC chance the next day. So, thought of preparing for them rather than going for JTM interview. Because any how even I had to go to Communications, I would go to IIT Bombay or Madras.

                        I will tell about the next part of VDTT in the next post.