Clock latency

Definition of clock latency (clock insertion delay): In sequential designs, each timing path is triggered by a clock signal that originates from a source. The flops being triggered by the clock signal are known as sinks for the clock. In general, clock latency (or clock insertion delay) is defined as the amount of time taken by the clock signal in traveling from its source to the sinks. Clock latency comprises of two components - clock source latency and clock network latency.

• Source latency of clock (Source insertion delay): Source latency is defined as the time taken by the clock signal in traversing from clock source (may be PLL, oscillator or some other source) to the clock definition point. It is also known as source insertion delay. It can be used to model off-chip clock latency when clock source is not part of the chip itself. 

• Network latency of clock (Network insertion delay): Network latency is defined as the time taken by the clock signal in traversing from clock definition point to the sinks of the clock. Thus, each sink of the clock has a different network latency. If we talk about the clock, it will have:
• Maximum network latency: Maximum of all the network latencies
• Minimum network latency: Minimum of all the network latencies
• Average network latency: Average of all the network latencies

Total clock latency is given as the sum of source latency and network latency. In other words, total clock latency at a point is given as follows:

       Clock latency = Source latency + Network latency

It is generally stated that for a robust clock tree, ‘sum of source latency and network latency for all sinks of a clock should be equal’. If that is the case, the clock tree is said to be balanced as this means that all the registers are getting clock at the same time; i.e., clock skew is zero.

Figure 1 : Figure showing source latency and network latency components of clock latency

Figure 1 above shows the two components of clock latency, i.e. source latency and network latency. Each flop (sink, in general) has its own latency since the path traced by clock from source to it may be different. The above case may be found in block level constraints in case of hierarchical designs wherein clock source is sitting outside the block and clock signal enters the block through a block port. It may also represent a case of a chip in which the clock source is sitting outside; e.g. some external device is controlling the chip. In that case, clock source will be sitting inside that device.

How to specify clock latency: In EDA tools, we can model clock latency using SDC command ‘set_clock_latency’ to imitate the behavior there will be after clock tree will be built. Using this command, we can specify both the source latency for a clock as well as the network latency. After clock tree has been built, the latency for the sinks is calculated by the tool itself from the delays of various elements. However, in case the clock source is sitting outside, it still needs to be modeled by source latency even after the clock tree synthesis. To specify clock latency for clock signal named ‘CLK’, we may use SDC command set_clock_latency:

                set_clock_latency <value> CLK

                set_clock_latency <value> CLK –source

First command will specify the network latency whereas the second command will specify the source latency for CLK.

Also read:

• Clock - the incharge of synchronous designs
• Timing corners - dimensions in timing signoff
• Ensuring glitch-free propagation of clock
• Clock switching and clock gating checks
• Can hold be frequency dependent

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