Regions of operation of MOS transistors

A Metal Oxide Semiconductor Field Effect Transistors (MOSFET, or simply, MOS) is a four terminal device. Figure 1 below shows the general representation of an N-MOS (for PMOS, simply replace N regions with P and vice-versa). MOS is a Voltage-controlled current source as the current through MOS is a function of relative voltage levels of its terminals. The relative voltages of gate, drain and source terminals (assuming bulk or substrate to be at same voltage as source) determine the magnitude of current flowing in MOS. In each of these regions, we can represent the current as a function of gate-to-source voltage (V_GS) and drain-to-source voltage (V_DS).

MOS transistor - a 4-transistor device

In a MOS device, the current flows on formation of channel of carriers between source and drain terminals. For this, voltage at gate terminal needs to be such that it attracts carriers of appropriate type towards itself. When sufficient carriers are attracted towards gate, channel is said to be formed. A current, then, flows between source and drain terminals depending upon the voltage levels of these terminals. The voltage level of substrate also impacts the magnitude of current as it also determines the level of carriers in the channel.

For an N-MOS device, the channel is formed by electrons. So, to attract electrons, gate voltage must be greater than source voltage. For the formation of channel, the difference between V_G and V_S (V_G – V_S) must be greater than V_th (threshold voltage of the MOS).

Threshold voltage is defined as the minimum difference in gate-to-source voltage needed for the formation of channel in a MOS device. For NMOS, V_th is positive as for channel formation gate needs to be at higher voltage as explained above. Similarly, for PMOS, V_th is negative as gate needs to be at lower voltage than source for channel to be formed.

On increasing gate voltage beyond threshold voltage, current through MOS increases with increasing gate voltage. Also, if we increase drain voltage keeping gate voltage constant, current increases till a particular drain voltage. After that, increasing drain voltage does not affect the current. Depending upon the relative voltages of its terminals, MOS is said to operate in either of the cut-off, linear or saturation region.

• Cut off region – A MOS device is said to be operating when the gate-to-source voltage is less than V_th. Thus, for MOS to be in cut-off region, the necessary condition is –

0 < V_GS < V_th                           -                       for NMOS

0 > V_GS > V_{th                                    -}                           for PMOS (as threshold voltage of PMOS is negative)

Cut-off region is also known as sub-threshold region. In this region, the dependence of current on gate voltage is exponential. The magnitude of current flowing through MOS in cut-off region is negligible as the channel is not present. The conduction happening in this region is known as sub-threshold conduction.

• Linear or non saturation region – For an NMOS, as gate voltage increases beyond threshold voltage, channel is formed between source and drain terminals. Now, if there is voltage difference between source and drain, current will flow. The magnitude of current increases linearly with increasing drain voltage till a particular drain voltage determined by the following relations –

V_GS ≥ V_th

V_DS < V_GS – V_th

The current is, then, represented as a linear function of gate-to-source and drain-to-source voltages. That is why, MOS is said to be operating in linear region. The linear region voltage-current relation is given as follows:

Id(Linear) = µ Cox W/L (Vgs – Vth – Vds/2) Vds.

            

Similarly, for P-MOS transistor, condition for P-MOS to be in linear region is represented as:

                        V_GS < V_th                        OR                         V_SG > |V_th|

            And      V_DS > V_GS + V_th                           OR             V_SD < V_SG - |V_th| 

• Saturation Region – For an NMOS, at a particular gate and source voltage, there is a particular level of voltage for drain, beyond which, increasing drain voltage seems to have no effect on current. When a MOS operates in this region, it is said to be in saturation. The condition is given as:

V_GS ≥ V_th

V_DS > V_GS – V_th

            The current, now, is a function only of gate and source voltages. 

                        Id(saturation) = µ Cox W/L (Vgs – Vth – Vds/2)²

Please note that this is just a primitive formula for Id in saturation region, and there are many advanced equations, modelings equations available for the MOSFETs of advanced nodes like 3 nm etc. And it is seen that the Id actually becomes linear with respect to Vgs. And also depends upon Vds as well.

Also read:

• Latch-up in CMOS devices
• Transmission gates
• Why depletion MOSFET cannot be used to create negative logic
• Defining a clock signal in VHDL 

Transmission Gates

Transmission gates represent another class of logic circuits, which use Transmission gates as basic building block. A transmission gate consist of a PMOS and NMOS connected in parallel. Gate voltage applied to these gates is complementary of each other (C and Cbar shown in figure 1). Transmission gates act as bidirectional switch between two nodes A and B controlled by signal C. Gate of NMOS is connected to C and gate of PMOS is connected to Cbar(invert of C). When control signal C is high i.e. VDD, both transistor are on and provides a low resistance path between A and B. On the other hand, when C is low, both transistors are turned off and provide high impedance path between A and B.

Figure 1: Transmission gate

A detailed analysis of working of transmission gates follows:

When input node A is connected to VDD and control logic C is also high, C = 1 : The output node B may be connected to capacitor. Let us say, voltage at output node is Vout.

For PMOS, Source of is at higher voltage than drain.

For NMOS, drain is at higher voltage than Source terminal.

 Hence, node A will act as source terminal for pMOS and as drain terminal for nMOS.

Drain to Source and gate to source voltages for nMOS are as :

                                                       V_DS,n = VDD – Vout

                                                       V_GS,n = VDD – Vout

For nMOS to be turned off, V_GS,n < V_th,n
                                             VDD – Vout < V_th,n
                                             Vout > VDD – V_th,n (Cut off region)

For Vout < VDD – V_th,n

V_DS,n > V_GS,n – V_th,n

i.e. will operate in saturation mode

Similarly for pMOS,

V_DS,p = Vout - VDD
V_GS,p = – VDD

For pMOS to be turned off V_GS,p > v_th,p threshold voltage for pMOS is –ve so pMOS will always be turned on.

For pMOS to operate in linear region, V_DS > V_GS – v_th,p

Vout – VDD > -VDD – V_th,p

Vout > - V_th,p

Vout > |V_th,p|

For Vout ≤ |Vth,p|, pMOS will be in saturation mode.

Unlike nMOS, pMOS remain turned on regardless of output voltage Vout

Thus PMOS will always be turned on, and as we know that PMOS Passes a strong 1 so voltage level high will be transmitted unattenuated.

Similarly,

When voltage at node A,Vin = 0 and C = VDD, node A will act as source terminal for nMOS and will act as drain for pMOS. nMOS will always be turned on hence level 0 will also be transmitted unattenuated.

when voltage at node A,Vin = VDD and C = 0 node A will act as drain terminal for nMOS and source terminal for pMOS

V_GS,n = 0 – VDD < V_th,n (cut off region)

Hence nMOS will be turned off

VGS,p = VDD – VDD = 0 > V_th,p (Cut off region)

Thus both transistor will remain off. Path between A and B will be an open circuit.

when voltage at node A,Vin = 0 and C = 0 : node A will act as source terminal for nMOS and will act as drain for pMOS.

V_GS,n = 0 – 0 = 0 <V_th,n (Cut off region)

V_GS,p = VDD – Vout

V_GS,p will be some positive voltage and threshold voltage of pMOS ,Vth,p is negative.

V_GS,p > V_th,p (Cut off region)

Hence both transistor will remain off and high impedance path exists between A and B.

Also read:

• Regions of operation of MOS transistors
• Enhancement and depletion MOSFETs
• Depletion MOSFETs and negative logic : why it is not possible
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