Defining a clock
signal in VHDL
Clock is the
backbone of any synchronous design. For test-benches, a clock is the most
desired signal as almost every design requires a clock. Going a bit deeper, a
clock signal is a binary signal that changes state every few time units. So,
defining a clock in VHDL is pretty simple, as shown below in the following code:
signal my_clock :
std_logic;
process
my_clock
<= ‘0’;
wait
for 5 ns;
my_clock
= ‘1’;
wait
for 5 ns;
end process;
The above code
defines a clock of period 10 ns with 5
ns high time and 5 ns low time, hence, 50% duty cycle. Since, we are assigning
a value to my_clock in the code, it can wither be defines as a signal or an
output. Most probably, clocks are defined in test-benches, hence, are internal
signals. High time and low time don’t always need to be same. You can always
define a clock that has different high and low times as shown below:
signal my_clock : std_logic;
process
my_clock
<= ‘0’;
wait
for 8 ns;
my_clock
= ‘1’;
wait
for 2 ns;
end process;
As we can see, now, my_clock has
a duty cycle of 80%; i.e. a high time of 80% and a low time of 20%.
Defining a clock
in this way, obviously, is not synthesizable as we are using delays in code,
and delays cannot be synthesized. Hence, this way of defining a clock can only
be used in a test-bench to test a piece of code. If you need to write a
synthesizable clock, then you have to use structural coding. The simplest of
clock generation circuits is a ring counter (a chain of inverters connected
back-to-back), but it will have a variable frequency clock because delay of
inverters changes on change in operating conditions.
