Worst slew
propagation is a phenomenon in Static Timing Analysis. According to it, the
worst of the slews at the input pin of a gate is propagated to its output. As
we know, the output slew of a logic cell is a function of its input slew and
output load. For a multi-input logic gate, the output slew should be different
for the timing paths through its different input pins. However, this is not the
case. This is due to the reason that to maintain a timing grapth, each node in the design can have only 1 slew. So, to cover the worst scenario for setup timing, the maximum slew at each output pin should be equal to that caused by the input pin having worst of the slews. The output slew calculated is on the basis of worst input slew, even if
the timing path for which the output slew is being calculated is not through
the input pin with worst slew. Similarly, the best of the slews is calculated based upon the effect of all the input pins for hold timing analysis. We can refer to it as best slew propagation.
Let us
illustrate with the help of a 2-input AND gate. As shown in figure below, let the
slews at the input pins be denoted as SLEW_A and SLEW_B and that at the output
pin as SLEW_OUT. Now, as we know:
SLEW_OUT
= func (SLEW_A) if A toggles leading to OUT toggling
And
SLEW_OUT = func (SLEW_B) if B toggles leading to OUT toggling
However, even though the timing
path as shown through A pin, the resultant slew at output SLEW_OUT will be
calculated as:
SLEW_OUT = func (SLEW_A) if func(SLEW_A) > func(SLEW_B)
= func (SLEW_B) if func(SLEW_B) > func(SLEW_A)
 |
| Figure 1: Figure showing worst slew propagation |
One may feel
this as an over-pessimism inserted by timing analysis tool. Path based timing analysis will not have worst slew propagation phenomenon as it calculates output slew for each timing path rather than one slew per node.
Similarly, for
performing timing analysis for hold violations, the best of the slews at inputs
is propagated to the output as mentioned before also.
Also read:
- Race conditions
- All about clock signals
- Propagation delay of logic gates
- Comparison between array, linked list and vector