Solution: The design in question is a combinational design with 32-bit input and 6-bit output as there can be maximum 32 1's and 32 stands "100000" in binary. Making a truth-table or K-map for this problem is not practical, so we have to take a modular approach. Let us divide the problem into detecting number of 1's among 4 bits and then adding the resulting numbers together providing the total count.
Let us first create a truth-table converting the number of 1's in a 4-bit stream into a 2-bit number. The resulting truth table is shown in figure 1.
|
Figure 1: Truth table for 4-bit count 1's circuit |
Solving the above for O2, O1 and O0 using K-maps, we get the expressions as shown in figures 2, 3 and 4 below.
|
Figure 2: Expression for O2 |
|
Figure 3: Expression for O1 |
|
Figure 4: Expression for O0 |
Thus, we have 8 instances, each counting the number of ones pertaining to respective 4 bits. The next thing we need is to add these 8 three-bit numbers to obtain the resultant total number of 1's in the 32-bit number we got. For this, we can again follow modular approach to add two numbers at a time until we are left with a single number. The block diagram of the complete solution is shown below in figure 5.
|
Figure 5: Complete block diagram of counting number of 1's |
Is there any way we can optimize this design?
ReplyDeleteHi
DeleteIn the modular approach we took, I dont think that more optimal design could be used. Otherwise, of course, yes. We could write an RTL code for the whole design and let synthesis tool optimize the design. For a human, I dont think it is feasible.