A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a repeater which repeats the signal it is receiving, just as there are repeaters in telephone signal transmission lines. You must have noticed that we have two kinds of buffers (or any logic gate) available in standard cell libraries as:
- Clock buffer: The clock buffers are designed specifically to have specific properties that are supposed to be good for clock distribution networks (clock trees). The specific properties that are required in an ideal clock tree buffer are given as below. However, it is not possible to attain these ideal properties for every buffer at every technology node. It may be only possible to get close to these properties.
- Equal rise and fall times
- Less delays
- Less delay variations with PVT and OCV
- Normal buffer/data buffer: For a data buffer, the above properties are usually less desired
Usually, we can say that following differences may exist between a clock buffer and a normal buffer:
- In SoCs, clock routing is done in higher metal layers as compared to signal routing. So, to provide easier access to clock pins from these layers, clock buffers may have pins in higher metal layers. That is, vias are provided in standard cell itself instead of necessitating on having in clock distribution network. For a data buffer, the pins are expected to be in lower layers only.
- Clock buffers are balanced. In other words, rise and fall times of clock buffers are nearly equal. The reason behind this is that if the clock buffers are not balanced, there will be duty cycle distortion in the clock tree, which can lead to pulse width violations as discussed in minimum pulse width violation example. On the other hand, data buffers can compromise with either of rise/fall times. In other words, they dont need to have PMOS/NMOS size to be 2:1; and hence, can be of smaller size as compared to clock buffers.
- Due to above reason, clock buffers consume more power as compared to normal buffers.
- Generally, you will find clock buffers with higher drive strength as compared to normal buffers. So that a clock buffer can drive long nets and can have higher fanouts. This helps clock buffers, and hence, clock trees to have less overall delays.
why clock buffers are consumes high power instead of normal buffer?
ReplyDeleteHi
Delete1. As discussed, clock buffers have symmetrical rise and fall delays, which causes PMOS to have higher size than normal buffer. Thus, the power is more because of bigger device size.
2. Clock buffers receive more toggling activity than normal buffers, thereby consuming more power.
Could you share some more detail with feature" Less delay variations with PVT and OCV", benefit for example?
ReplyDeleteHi
DeleteOne of the examples may be that a clock buffer may have wires of greater width than a normal buffer so that the width variations are not that prominent.
Hi,
ReplyDeleteHow doubling the width of pmos to nMOS ratio.helps in making equal rise and fall times of clock buffers
Hi Smita
DeletePMOS usually have higher resistance than NMOS due to lesser mobility of holes. And we know that rise and fall times is essentially time taken to charge the capacitor at the output, given by Q = I * t. Now, I depends upon R, the value of resistance. In simplistic terms, to make rise and fall times of the gate equal, we will need to have PMOS of higher width so that resistance of PMOS is comparable to that of NMOS. In some technology, this factor may be two. This is where doubling number comes from.
hat basis you tell pmos and nmos size is 2:1 ratio in clock buffer and why clock has equal rise and equal fall
ReplyDeleteHi
DeleteWhen I said that pmos & nmos size should be 2:1, there I assumed that PMOS to NMOS substrate resistivity is in the same ratio. So, in order to pass same current, the size of PMOS required is twice (this is a very simple approximation taken in most of the texts).
Now, under most scenarios, a clock buffer is expected to not distort clock pulse. This is possible only if it has equal rise and fall delays. So, a clock buffer design should be done taking this into consideration.
I would recommend you to go through this post to help you understand better.
http://vlsiuniverse.blogspot.in/2017/11/minimum-pulse-width-violation-example.html
Hi, what you mean clock buffer is it pair of inverters connected back to back?
ReplyDeleteHi, what you mean clock buffer is it pair of inverters connected back to back?
ReplyDeleteHi
DeleteAny buffer in CMOS is a pair of inverters connected back to back, since you cannot create non-inverting logic with enhancement type of MOSFETs.
The special thing in clock buffers is mentioned in the post that differentiate it from normal buffers.
Regards
Gourav
Hi, If the clock buffer has so many strengths, why in the design do we not use the entire clock buffer, but have to use the data buffer?
ReplyDeleteHi, there is a very simple reason behind this. To make clock buffers symmetrical, you have to sacrifice area and power. So, in order to save area, every buffer in the design cannot be a clock buffer. :-) It is like saying, you dont use granite in every construction even though it is very strong and durable.
ReplyDeleteHi, very interesting article. I wanted to know more about this clock buffer because, wandering around the internet, I can't find anything of what it's like inside. Some say it is made up of two inverters in series and some say it is a non-inverting amplifier. Could you tell me something about it or direct me to a resource that explains the clock buffer very well and can clarify my doubts? Thank you
ReplyDeleteHi, can you share some insights into what kind of technology you are into? Is it asic design, foga design or something else?
DeleteIt is xilinx FPGA
DeleteIn my opinion, you should be able to get the information from datasheet of the FPGA. However, there is a 99% chance that the clock buffer will be 2 inverters connected back-to-back even in FPGA, since CMOS technology doesnt allow a non-inverting amplifier. Its just that the transistor sizes will be huge to allow 1. long nets to be driver 2. less variation
Delete