Zero cycle path: A zero cycle timing path is a representative of race condition between data and clock. A zero cycle path is one in which data is launched and captured on the same edge of the clock. In other words, setup check for a zero cycle path is zero cycle, i.e., it is on the same edge as the one launching data. Hold check, then, will be one cycle before the edge at which data is launched. Figure 1 below shows the setup check and hold check for a zero cycle timing path.
Figure 1: Setup check and hold check for zero cycle paths |
How to specify zero cycle path: As we know, by default, setup check is single cycle (is checked on the next edge with respect to the one on which data is launched). If the FSM requires a timing path to be zero cycle, it has to be specified using the SDC command "set_multicycle_path".
Figure 2: Default setup and hold checks for single cycle timing path |
set_multicycle_path 0 -setup -from <startpoint> -to <endpoint>
where <startpoint> is the the flip-flop which launches the data and <endpoint> is the flip-flop which captures the data. In other words, as viewed from application perspective, zero cycle path is one of the special cases of a multi-cycle path only. Above multicycle constraint modifies the setup check to be zero cycle. Hold check also, shifts one edge back.
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Great material! Very handy cheatsheets for circuit designers. Excellent!
ReplyDeletehii...if there are violations in setup for zero cycle path...how that can be closed? because we dont get enough margin.?
ReplyDeleteHi Deva
DeleteThat will be a race condition between clock and data. The only possible solution is to have skew more than data path.
Why would this type of a check and MCP definition be needed ?
ReplyDeleteIt all depends upon the architecture, and an RTL designer can come up with such a case. In reality, zero cycle setup paths are not so uncommon.
Delete