16x1 mux using 4x1 muxes

Implementing 16:1 multiplexer with 4:1 multiplexers: A 16x1 mux can be implemented using 5 4x1 muxes. 4 of these multiplexers can be used as first stage to mux 4 inputs each with two least significant bits of select lines (S0 and S1), resulting in 4 intermediate outputs, which, then can be muxed again using a 4:1 mux. The implementation of 16x1 mux using 4x1 muxes is shown below in figure 1:

Figure 1: Implementing 16:1 mux with the help of 4:1 multiplexers

The above approach assumes that all the inputs are of same priority as regards timing. Can you think of a solution which involves timing and prioritizes some of the inputs? A hint for you is that the solution will require 5 select lines instead of four.

Also read:

• XNOR gate using NAND
• 2:1 mux using NAND gates
• Implement 3-inputs gates using 2:1 muxes
• Time borrowing in latches
• Latch using 2:1 mux