Technology scaling factor
For instance, you will find technology nodes as 180 um 90 um, 65 um, 45 um, 32 um, 22 um and so on..
*Source - Digital integrated circuits - A design perspective by Jan M Rabay
Working in Infosys - A Dream Come True
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| The Lavish Building of Infosys - Mysore |
Post Btech, many would be getting into the service based companies like Infy, TCS, Capgemini, IBM etc. I would like to share few important information, that would be really useful for many and it would be good to know these before joining.
With the frustration that I couldn't get much with my GATE Rank and the call letter of Infy coming too early made me join Infosys 2 days immediately after my college.
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| In Infosys Multiplex with One of my good friends - Praveen Vukoti |
Training : - Mysore
We were given training in Mysore. The training consists of Generic and Stream part. Tell you what, this is the best ever platform that I have ever seen for learning things. The training is too worthy. One never feels like missing any thing there.
The resources are awesome and even if you are not expertise in JAVA, HTML or so, you will be made so , given the resources and the quality of teaching. Yes, it is a bit pressure, having had to sit in class from 9 a.m to 6 p.m., but then it is worthy.
Industrial oriented training given by Infosys is awesome. I don't know much about the other companies but I hope even they maintain standards.
Having completed, generic training which includes - JAVA, HTML, CSS, JS, ORACLE,SOFTWARE ENGINEERING, you will be given streams.
Those who couldn't clear the the Generic part will be given 3 chances to clear their exams and post that they will be given streams, (if cleared )and if not,they will asked to leave the company ( sad right)
The streams are random and this is a bit negative point here in Infosys.
What ever type of person you are, may be a software freak or hater of software, still every one will be enjoying the training because of the standards of teaching and the resources and more than any thing else the fear of getting failed.. ( Of course exams will be there)
Facilities
Accomodation: Ultimate like a five star hotel. But don't dream too much because you will hardly have time to sleep there.
Food : U have food courts where the food is served of different regions and you can enjoy it at reasonable prices
Gym & Swimming Pool: Yes every thing apart from these also there like medical facilities, basket ball court, badminton, Table tennis, cricket and much more.
One thing that I can assure you is that you will be blown out with the beauty of the campus.
I will post few pictures of Infy Mysore DC. in the next post.
If some one has any individual doubts, you can always comment downside and I will answer your queries.
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| A Big Journey in My Life - Journey to Mysore |
BARC & IIT Bombay RA Experience
Went to Bombay a day before. Stayed in IIT Bombay because I had few facebook friends. To my luck , even they had BARC Interview. We all went there. There was initially a check up of all the certificates and to and from tickets for travel allowance. The interview went on like this
1. Graph of Voltage across capacitor vrs time with different values of R,L,C in series RLC Circuit.
2. Super Diode
3. A lot of confusing questions on whether some Mosfet is depletion or enhancement type.
4. Set up and Hold up time
5. Signals and Systems questions were mostly on finding the Fourier series and transform based on symmetry.
6. Some quality Control System questions.
With this.. My tour of India completed.
Starting from Bangalore to Madras to Delhi to Bombay.....................
Before putting some thing else, I want to summarize as to what all offers I had in my hand
1. IIT Bombay - Communications ( 1st round) and Electronics Systems ( 4th round)
2. IIT Madras - Communications ( 1st round)
3. IIT Delhi - IEC, VDTT
4. IIT Kharagpur - Micro Electronics
5. IISC Bangalore - Communications and Networking
The below given experience is by my friend K. Bharadwaj. I needn't had to go to IIT Bombay RA. He have put his thoughts. He tasted the success in IIT Bombay RA and I have put his experience.
M.Tech (EE)IIT BOMBAY (RA) Experience
It is usually very difficult getting VLSI in old IIT's for ranks above 200(my rank is 295 and score 803 in EC).For such people,IITB provides a golden oppurtunity with M.Tech as RA(Research Assistant).It's a 3 year course but is nowhere different to two year M.tech as TA(Teaching Assistant).Curriculum,Coursework and placements are all same except that RA has to spend one more year.As an RA,one has to take less courses per semester(3 as against 5 for TA) but has to spend 20 hours of work per week as against 8 hours of work for TA.There are two kinds of Research assistants
1.Institue RA
-One has to work in labs like electronics lab,VLSI lab to help undergraduate students in performing experiments.These are concerned with day to day activities of lab including maintainence.Even System administrator comes under this RA.
2.Project RA
-Professors have funded projects from various sources.As a project RA,one has to assist these professors in project and in administrative work also as told by respective guide.
Now,the difference between them is in chosing guide.Project RA will be assigned a guide at selection and cannot be changed.He is expected to do his thesis work in same area as project alloted while Institute RA has the freedom of choosing guide.
Selection Process :
Cutoff is put in gate score and are called.This year(2015),cutoff is 660(GEN),596(OBC),440(SC/ST).It means ranks upto 1200 can also be called in GEN
There will be a written test and Interview as part of selection process.
Written Test:It has objective type questions in which some may require answers in one or two sentences.Time duration is 2 hours
Consisted of 3 sections
Section 1 consists of MATHS,APTITUDE,CONTROL SYSTEMS,ELECTRICAL MACHINES (50 marks as far as i remember)
Section 2 consists of LINUX Basics(commands,networking ),Communication,DSP questions(50 marks ..or may be 60.. i dont remember exactly)
Section 3 consists of Analog ,digital and electronic devices (50 marks)
There is no need to attempt all sections.Because it is not expected for a core electrical guy to know communications and vice versa.It is essential to score in the area for which you gave preference.Questions level were easy-medium but time was the constraint.this year,paper was lengthy enough that scoring 50 in whole paper is great.I guess my score would be around 45
Now shortlisting happens on following criteria
Institute RA- 50 % gate score ,50 % written test
Project RA-75 % gate score,25 % written test
Till last year 2:1 people were called for the interviews for the number of positons available.But this time it was 3:1.This year number of positions for institute RA are 36(5 were for only electrical)
and 21 for Project RA(5 were pure electrical projects).120 odd people were shortlisted for Institute RA whereas 63 for project RA(around 300 people gave written test).Your name can appear in both lists but will be interviewed only once in which you have to indicate preferences.
This is atleast 2 day process in which first day will be written test.Resullts will be in website by Night.Next day,we assembled at hall and we were given forms for giving preferences in Institute RA(Electronics lab,VLSI lab,System administrator,Communication lab).Projects(abstracts were given to us) seperately for institute RA and Project RA.we were then addressed by HOD who surprised us with a new proposal this year to check laboratory skills for people who preferred electronics lab in 1st or 2nd choices.We were taken to WEL lab and were given an experiment to perform.It was implementing 3 bit counter using a 4 bit counter (not the usual kind but its easy.just that idea has to strike)and connecting it to a DAC circuit given in question and verifying with theoritical values.
INTERVIEW :There were 16 panels and we are alloted based on our preferences in the form filled earlier.Each panel had 2 members.If you are shortlisted for both institute as well as project(and dual degree (mtech +phd )also had interviews in same timings.You have to write same test as RA if u have applied and have been invited for that also),the panel asks you preference .I preferred project RA as i had interest in a proj 'chip design for Physiological monitoring(healthcare)' and had previous experience with my mini project in same area.I was asked to introduce myself and I told about my education and projects I did as major and mini.They were interested and asked me about the circuit i used for mini project which had biasing,filtering and amplication.I was asked about the opamp used in my project and why was it specifically used(it was noiseless).We basically had a discussion rather than being interviewed.Then the professor asked me a basic RC filter question and asked me to draw outputs on R and C for a square wave input.Then asked when it would function as Integrator and differentiator and what happens if the case is opposite(RC>>T,RC<<T).All this took around 30 mins .Only one prof asked me all this.I got to know that other prof is asking about digital questions if we mentioned digital as interest.They asked me what I was doing for the last one year as i was already passout last year.Thats all.They said they were done.So simple it seems na ;).It was the simplest interview of all the ones i had.They were asking only basic questions.So if you have good gate score and performed reasonable well in written test and interview you can get seat easily.If you have less gate score,dont worry but perform well in written test and interview.Results will be annouced in a week or two.
I am here by putting up few links that may be useful for students
I am here by putting up few links that may be useful for students
http://asic.co.in/Index_files/Digital_interview_questions1.htm ( Some very good questions with explanations for Digital electronics. Will also help you clarify your concepts )
http://asic-soc.blogspot.in/ ( Digital questions )
http://www.allinterview.com/Interview-Questions/Electronics-Communications.html ( Open in Mozilla or IE )
Go and have a blast @ GATE.
Finally, hope this journey was good.....
Any query please feel free to ask and subscribe to this blog for more information.
IIT Delhi - Part 5 - Interview Experiences
The results came out after 3 days.
Yes. I tasted bitter in terms of loss of Texas and Cadence. But these were not un happy scenes for me because I knew how the things went inside in the interview.
But to my happiness finally, I got selected for VDTT - with the external sponsorship from Cypress Semi Conductors. Also, I got IEC.
Thank God..... So finally I got selected for something through rounds of interview..
Thanks..
The next post would be about the only Govt Job that I attended - BARC.
It is located in Bombay. It is one of the finest things. Although it is very good program but from the ECE point of view, all it would leave you is with a satisfaction that you are having Govt Job and nothing much.
Lets go to Bombay and taste some wada pav............................
IIT Delhi - Part 4 - Interview Experiences
I know many of you would be waiting as to what happened and how things went..
I was called for Cypress Semicondutors Interview
Cypress Interview Experience:
He asked me about hold time, set up time constraints and how they come into picture and what will you do to mitigate with it. Actually these questions would have been new to most of the Btech guys and even they were new to me also, had I not gone to IISC Bangalore.
They never asked these, but I got it here. So that's the reason, I would always ask people to attend interviews. Because you never know what happens when and what is coming your way.
It was followed up with some normal questions on comparators. I was asked to design a comparator using MOSFET.
Then few normal questions on CMOS Inverter. I was going well.
Then other questions about BJT. Few questions on Body Effect, different regions of operation of MOSFET and BJT.
Also the last question was "Why Mtech , leaving job in a company"
I some how felt very confident about the interview. I immediately called up my father and told that I would be in easily.
Cadence Interview
They had 2 panels - One for software and other for Analog profile. I some how, unable to recongize the labels of the panels, went to software profile. They asked C, Linked Lists, Data Structures.
I kept mum for a while and answered few things. But I never felt I was in.
They offered me a bottle of Yummy Apple Juice. I couldn't resist taking it, after all atleast Apple Juice should be for me, if not a position in Cadence.
Texas Interview:
I was shocked first of all as to how and why Texas called me because I kept them as 4 th preference. There was only 1 question that he was asking me since the starting. I and the person were discussing only about the same circuit. I could not solve to the extent to which he needed. It was again about transient analysis in Network Theory.
Then there were few questions on CMOS Inverter and the Body Effect. But they were too much beyond my capability.
Qualcomm didn't call me.
I was called for Cypress Semicondutors Interview
Cypress Interview Experience:
He asked me about hold time, set up time constraints and how they come into picture and what will you do to mitigate with it. Actually these questions would have been new to most of the Btech guys and even they were new to me also, had I not gone to IISC Bangalore.
They never asked these, but I got it here. So that's the reason, I would always ask people to attend interviews. Because you never know what happens when and what is coming your way.
It was followed up with some normal questions on comparators. I was asked to design a comparator using MOSFET.
Then few normal questions on CMOS Inverter. I was going well.
Then other questions about BJT. Few questions on Body Effect, different regions of operation of MOSFET and BJT.
Also the last question was "Why Mtech , leaving job in a company"
I some how felt very confident about the interview. I immediately called up my father and told that I would be in easily.
Cadence Interview
They had 2 panels - One for software and other for Analog profile. I some how, unable to recongize the labels of the panels, went to software profile. They asked C, Linked Lists, Data Structures.
I kept mum for a while and answered few things. But I never felt I was in.
They offered me a bottle of Yummy Apple Juice. I couldn't resist taking it, after all atleast Apple Juice should be for me, if not a position in Cadence.
Texas Interview:
I was shocked first of all as to how and why Texas called me because I kept them as 4 th preference. There was only 1 question that he was asking me since the starting. I and the person were discussing only about the same circuit. I could not solve to the extent to which he needed. It was again about transient analysis in Network Theory.
Then there were few questions on CMOS Inverter and the Body Effect. But they were too much beyond my capability.
Qualcomm didn't call me.
IIT Delhi - Part 3 - Interview Experiences
So the day started with the continuation of the previous day.
VDTT is a sponsored program, where in the first round of Interviews will be conducted by the IIT Delhi Professors and the second round of interviews will be done the by Sponsors and the Internal MHRD Project Profs.
VDTT 2nd round:
So although, it was supposed to start @ 9 am in the morning, it started after lunch. So in the mean while, I went to IEC interview (skipping my lunch). To my luck, there were the few professors who interviewed me in VDTT first round. They recognized me and asked me whether I was through in the 1st round of VDTT. I replied kindly that the first round I got in and the next rounds are going on.
The Professors were impressed with my rank and also few questions normally about MOSFET were asked and I was told at that point of time only that you are offered IEC and if you don't fare well in VDTT next round, take it or else leave it fastly.
With the first success, I walked into VDTT interview room.
There were too many presentations.
Companies : Qualcomm, Texas, Cypress, Cadence.
Projects: Nanoscale Devices, Smart Cane/Refreshable Braille Display,Mass Spectrometer
So out of the 300 odd students that came into the initial phase, roughly 25 students were in for the next round and roughly 10 seats are available..
Lets fight...
We were asked to keep the preferences to the 7 Sponsors. I have kept Cypress in the top and followed with Cadence, Qualcomm, Texas.
Frankly I was afraid with Texas because of the previous experience in IIT Madras. At the same time, I was dis appointed that I was un prepared to attend the Interview of Qualcomm because I was not in touch with Communications for a while.
In the next post, I will share my Interview. How things went. ..
How was the story of my failure agian... and a success story from it..
VDTT is a sponsored program, where in the first round of Interviews will be conducted by the IIT Delhi Professors and the second round of interviews will be done the by Sponsors and the Internal MHRD Project Profs.
VDTT 2nd round:
So although, it was supposed to start @ 9 am in the morning, it started after lunch. So in the mean while, I went to IEC interview (skipping my lunch). To my luck, there were the few professors who interviewed me in VDTT first round. They recognized me and asked me whether I was through in the 1st round of VDTT. I replied kindly that the first round I got in and the next rounds are going on.
The Professors were impressed with my rank and also few questions normally about MOSFET were asked and I was told at that point of time only that you are offered IEC and if you don't fare well in VDTT next round, take it or else leave it fastly.
With the first success, I walked into VDTT interview room.
There were too many presentations.
Companies : Qualcomm, Texas, Cypress, Cadence.
Projects: Nanoscale Devices, Smart Cane/Refreshable Braille Display,Mass Spectrometer
So out of the 300 odd students that came into the initial phase, roughly 25 students were in for the next round and roughly 10 seats are available..
Lets fight...
We were asked to keep the preferences to the 7 Sponsors. I have kept Cypress in the top and followed with Cadence, Qualcomm, Texas.
Frankly I was afraid with Texas because of the previous experience in IIT Madras. At the same time, I was dis appointed that I was un prepared to attend the Interview of Qualcomm because I was not in touch with Communications for a while.
In the next post, I will share my Interview. How things went. ..
How was the story of my failure agian... and a success story from it..
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