Below we list few of our posts related to clock jitter and duty cycle variation. Happy learning.
- Clock jitter: Disusses the definition and types of clock jitter.
- Can jitter in clock effect setup and hold violations? : Discusses cases of setup and hold slack calculation where jitter in clock path can play a role
- Duty cycle of clock: Discusses the definition of duty cycle and how it impacts timing slack of timing paths.
- Duty cycle variation: Discusses in detail basics of duty cycle variation and its timing implications.
- Duty cycle variation of inter-clock timing paths: Discusses the implication of duty cycle variation in case of root (master) clock to generated clock paths and inter-generated clock paths.
- Duty cycle degradation: Discusses the factors responsible for duty cycle degradation
- How to fix min pulse width violation: Discusses a few techniques to tackle min-pulse-width violations.
- Duty cycle care-abouts for clock paths in reset assertion - Discusses how reset assertion can alter the duty cycle of clock, and what needs to be taken care of.
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