Duty cycle: Duty cycle of a clock is defined as the fraction of a period of clock during which the clock is in active state. Duty cycle of a clock is normally expressed as a percentage. For instance, figure below shows a clock having an active state of '1' stays low for 2 ns during its period of 10 ns. It is, therefore, said to have a duty cycle of 20%.
How duty cycle impacts timing: Duty cycle of clock plays a big role in timing closure of designs. We need to consider following factors related to duty cycle variation while timing:
- Half cycle timing paths: If there are both positive and negative edge-triggered flip-flops in the design, duty cycle of the clock matters a lot. For instance, if we have a clock of 100 MHz with 20% duty cycle; For a timing path from positive edge-triggered flip-flop to negative edge-triggered flip-flop, we get only 2 ns for setup timing for positive-to-negative path and 8 ns for negative-to-positive path as compared to 10 ns for a full cycle path. However, if the same clock had duty cycle of 50%, we would have got 5 ns for the same half cycle timng path.
- Minimum pulse width requirements: At high frequencies, duty cycle matters a lot. For instance, every sequential element has requirement of minimum pulse width that should reach it (read this). If the duty cycle of the clock is not close to 50%, we are limited in providing high frequency even if we are capable of meeting timing at even higher frequencies. Let us take an example. If the minimum pulse width requirement of a flip-flop is 500 ps, then with 50% duty cycle clock, we can use a clock of 1 GHz (1 ns clock period). But if we use a clock of duty cycle of 20%, we cannot use a clock greater than 400 MHz.
With the above things in mind, it makes sense to use a clock with duty cycle as close to 50%. However, in many scenarios, it may not be feasible to do so. So, one needs to decide the priorities; i.e., architecture complexities vs timing complexities. Generating a divided clock of 50% duty cycle is not always possible and there are a few complexities involved in architecture. For instance, clock waveform synchronization between the clocks if there are multiple dividers. Also, for odd division factors like divide_by_3 etc., we need more complex divider circuitry than what may be required for divide_by_2 or divide_by_4 etc.
Can you please help elaborate on this "But if we use a clock of duty cycle of 20%, we cannot use a clock greater than 400 MHz"
ReplyDeleteHi
DeleteThe flip-flop that is going to consume the clock has a minimum pulse width requirement of 500 ps, so we cannot have a pulse width less than 500 ps. 500 ps is 20% of 2.5 ns, so the clock period must be greater than 2.5 ns. In other words, clock frequency must be less that 400 MHz.
Thank you for the explanation to the query above.
DeleteI'm glad that you found it useful.
DeleteHow about duty cycle more than 50%? Since min pulse requirements are met with more than 50%, is duty cycle of 90% allowed? what are the downsides?
ReplyDeleteHi
DeleteWhat you are missing here is that there is also a min-pulse-width requirement in the other direction; i.e. there are both high pulse and low pulse requirements. So, if you provide a duty cycle of 90%, it means low pulse is only 10% and most probably will limit the design frequency.