IIT Delhi - Par1 - Interview Experiences

Before going to Delhi, just 2 days back I got Kharagpur VLSI, so I was a bit uncertain whether I will be going because I was comfortable with VLSI in top 5 IITs. But then to my luck, the reservation was confirmed and I along with 2 others have gone there. From Hyderabad, it almost took 30 hours journey.

I had a lot of Interviews in IIT Delhi – IEC, VDTT, JTM, Computer Technology.

We got into the college 1 day before the Interview. IIT Delhi is good in one aspect that it doesn’t have written tests. I have not been qualifying the tests so far may be because they were written test  ( Jokes are excuses some times)

I have a friend Roopesh Sharma there ( JTM Student and AIR 245 in Gate 2014) . The hostels in IIT Delhi are not that great in terms of look. Food is ok. My friend had luckily made me familiar with few seniors of IEC and VDTT.

I had conversation with few persons of both IEC, VDTT. I came to know about the process but then I had to appear for the process.

VDTT Interview : 

                            Initially they verified our documents and divided us into few groups and each group for each Interview panel. Mine was Panel 2. Initially every panel students were coming out but in our panel there was no one who even went inside. I was the first person as per sequence in my panel.

After a while, I was asked to come into. The Panel had 2 Professors, old enough to make me afraid. I greeted them and even they followed it up with a nice little smile, that made me feel a bit relaxed.

I was asked the following questions.

                                    1. Draw CMOS Inverter

                                    2. In the same diagram, now ground and power supply are exchanged?

                                     3. Implement Y = AB+C+D (whole bar) in NMOS,PMOS,CMOS logics

                                       4. If I add 2 sin signals with one of them having frequency f1 and other 2*f1                                               or say some 1000*f1. Then draw the resultant as a diagram.

                                            5. Why CMOS. Why not NMOS or PMOS.

The results where supposed to be announced in the evening. 

               I was waiting upto evening.

I was in an unknown status. Going by my heart, I thought I was in. But then Bangalore and Madras kept me thinking and reminding about my luck again and again...

JTM Interview :

                            Didn't attend the Interview because some how I was confident about VDTT and also even if I don't do VDTT well, I had IEC chance the next day. So, thought of preparing for them rather than going for JTM interview. Because any how even I had to go to Communications, I would go to IIT Bombay or Madras.

                        I will tell about the next part of VDTT in the next post.

                             

                   

IIT Madras - Interview Experiences

Yes. After the failure of IISC Bangalore, I went to IIT Madras. I came here for Texas Sponsored MS.

It is one of the very good programs in IITs in the field of VLSI. IIT Madras is best for some one interested in Analog Research.  I was prepared for a tough fight. 

I knew mentally that It would be very difficult for me to clear the rounds because the number of people whom they will call is all ECE Rankers < 1000 and all Instrumentation and Electrical guys with Ranks< 750.

There is no reservation for this program. Luckily I haven't had any.

I got there on May 1^stitself. I had a friend Charan working in TCS. Both of us roamed around the city and went to sea shore and few other places. It was as if I came there for some other reason. But thanks to him, atleast roamed a lot in Chennai. Thanks for him for a lovely care.

Next day on May 2^nd , I went to the College – IIT Madras. In the presentation by the Texas team, they have really made us get goose bumps for the company it is. It produces diverse products and today Texas is in the top position in Analog research and IIT Madras is like heaven for analog research. 

It has 3 gods of Analog – Nagendra Krishnapura, Anirudhan, Shanti Pavan.  Texas came with an offer of employment of 16L after successful completion of MS, although nothing is assured. They will also give us higher stipend of 20K for the first year and 30K for the next 2 years.  

I went to the written test. I was shocked to see the questions. They were not easy but neither were they out of box. I can assure you u can never come across such questions any where in any question bank.

Most of the guys were in the same mood. Don't know what to comment. They were such questions which required us to be theoretically Mr. Perfect, nothing less.

I will update all the questions once I sit back to write all those in a notebook. In the mean while you can refer to the given link. Actually One thing is that Texas will only ask transient analysis and Analog Electronics to a very deep level.

http://www.ee.iitm.ac.in/vlsi/tiiprogram/faq 

But this was a bit too tougher on my part. I knew that syllabus is Network theory and Analog Electronics. But I could not clear the written round due to my lack of understanding things in even perfect way.

It required a lot of mastery of the subject much better than mine.

But learnt again that I still need to improve.

               With low levels of Confidence and may be in a spot of bother whether I will not be able to manage to get VLSI seat through Interview, I read more for the next time... 

                            Chalo Delhi. next