In our previous post, Setup and hold – the state machine perspective, we discussed how setup and hold can be defined in respect of state machines. Interestingly, there is another perspective of setup and hold – that in repect to devices, known as setup and hold time requirements. For a device, (for example a flip-flop, a latch or an SoC), setup and hold times are defined as:
Setup time: Setup time of a device is defined as the minimum time before the clock edge the data should be kept stable so that it is reliably sampled by the clock.
Hold time: Hold time of a device is defined as the minimum time after the clock edge the data should be kept stable so that it is reliably sampled by the clock.
In other words, every device has a setup and hold window surrounding the active clock edge within which data should be kept stable. As is shown in figure 1, brown line represents the active clock edge, blue line represents setup window and red line represents hold window. As is shown, data can toggle at any time except between setup and hold windows. Toggling of data between setup-hold window means flip-flop might go into metastable state and the output of flip-flop does not remain predictable.
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| Figure 1: Setup and hold checks |
Origin of setup and hold timing requirements: Let us consider a positive edge-triggered flip-flop. Figure 2 shows a most simplistic circuit for a practical flip-flop. Inverters I1, I2 and Transmission gates G1, G2 constitute master latch and I3, I4, G3, G4 constitute slave latch.
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| Figure 2: A typical practical circuit for negative edge-triggered flip-flop |
Figure 3 below shows the origin of setup time requirement. For data to get latched properly, it should complete the feedback loop of master latch before the closing edge of clock at transmission gate G4. So, setup time requirement of the flip-flop is:
Tsetup = TG3 + TI1 + TI2 + TG4
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| Figure 3: Figure demonstrating delays constituting setup check |
Similarly, figure 4 below shows the origin of hold timing requirement. For data to get latched properly, the next data should not cross inverter I1. So, hold timing requirement of the flip-flop is:
Thold = -(TG3 + TI1)
In other words, hold time is the minimum time required for the data to change after the clock edge has passed so that new data does not get captured at the present clock edge.
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| Figure 4: Delays constituted in hold check |
Thus, in this post, we have discussed the origin of setup and hold checks for a device.
I think thold=0 . For negative edge triggered flipflop thold is time after the negative edge for which the input should be held stable. As soon as the clock goes low G3 turns off and any change in input won't be reflected. So hold time should be 0.
ReplyDeleteHi
DeleteIn my opinion, even if data crosses the transmission gate; until it reaches the output of inverter, the inverter will again cause the transmission gate output to go to previous value after clock goes off.
Why is the hold time value negative here?
ReplyDeleteHi Sriram
DeleteI recommend you go through following link. We can discuss in case of any queries :-)
https://vlsiuniverse.blogspot.com/2017/01/negative-hold-time.html#:~:text=Negative%20hold%20time%3A%20Similarly%2C%20when,waveform%20for%20negative%20hold%20time.&text=We%20have%20discussed%20above%20theoretical,zero%20and%20negative%20hold%20time.