STA problem: Checking for setup/hold violations in a timing path

Problem: Figure 1 below shows a timing path from positive edge-triggered register to a positive edge-triggered register. Can you figure out if there is any setup and/or hold violation in the following circuit?

Figure 1: A sample timing path

Solution:

To check if a timing path violates setup and/or hold, we need to check if they satisfy setup and hold equations. A violating timing path has a negative setup/hold slack value.

The above circuit has a positive clock skew of 1 ns (as capture flip-flop gets clock 1 ns later than launch flip-flop).

Let us first check for setup violation. As we know, for a full cycle register-to-register timing path, setup equation is given as:

T_ck->q + T_prop + T_setup - Tskew < T_period

Here,

T_ck->q = 2 ns,  T_prop (max value of combinational propagation delay) = 4 ns,  T_setup = 1 ns, T_period = 10 ns, Tskew = 1 ns

Now, T_ck->q + T_prop + T_setup  = 2 + 4 + 1 - 1 = 6 ns < T_period

So, the above circuit does not have a setup violation. The setup slack, in this case, will be given as:

SS = T_{period -} (T_ck->q + T_prop + T_setup - Tskew₎ 

SS = +4 ns 

Since, setup slack comes out to be positive, this path does not have a setup violation.


Now, let us check is there is a hold violation for this timing path. Hold timing equation is given as:

T_ck->q  + T_prop > T_hold + T_skew

Here,

T_ck->q  =  2 ns, T_prop (min value of combinational propagation delay) = 2 ns, T_hold = 2ns, T_skew = 1 ns

 Now, T_ck->q  + T_prop = 2 ns + 2 ns = 4 ns

And T_hold + T_skew = 2 ns + 1 ns = 3 ns

Now, 4 ns > 3 ns, so this circuit does not have a hold violation. The hold slack, in this case, will be given as:

HS = T_ck->q  + T_prop  - (T_hold + T_skew)  = +1 ns

Since, hold slack comes out to be positive, this path does not have a hold violation.

Also read:

• Finding the maximum frequency of operation of a timing path
• Setup and hold interview questions