Liberty format : an introduction

What is liberty format: Liberty format is an industry standard format used to describe library cells of a particular technology. A cell could be a standard cell, IO Buffer, complex IP etc. Library cell description contains a lot of information like timing information, power estimation, other several attributes like area, functionality, operating condition etc. Speaking more technically, liberty format is a format to represent timing and power properties of black boxes (which we cant descend into). Liberty is an ASCII format, usually represented in a text file with extension ".lib". In this section, we will discuss timing aspects (delay and transition times) related to liberty format.

How is liberty file populated with data: The cells represented through liberty files are first simulated under a variety of conditions representative of actual design conditions that the cell may be exposed to. This process is known as characterization of library cells. As a very simple example, the delay of an inverter depends upon the input transition time and output load capacitance seen by it. The inverter will be characterized for a range of input transitions and output load capacitances. This characterization data, will then, be put into liberty in the form of a look-up table representing delay values at different transition times and load values.

To understand the different constructs related to timing in liberty file, let us take example of inverter. Rising transition at the input of inverter produces falling transition at the output of inverter and vice-versa. Hence there are two types of delay :

1. Rise delay : It is the propagation delay (see definition) between output and input when output changes from 0 to 1.
2. Output fall delay : It is the propagation delay between output and input when output is changing from 1 to 0.

In the real world, signal does not change its state from 0 to 1 or 1 to 0 abruptly. It takes some time to change its state. Hence, delay is measured based upon the threshold points. Threshold points in the liberty file are specified as below:

# threshold point of input falling edge
input_threshold_pct_fall : 50.0 ;

# threshold point of input rising edge
input_threshold_pct_rise : 50.0 ;

#threshold point of output falling edge
output_threshold_pct_fall : 50.0 ;

#threshold point of output rising edge
output_threshold_pct_rise : 50.0 ;

NOTE : these values are in percentage. e.g. If vdd is 5v then all of the above values will be 2.5.

So, Output rise delay is time difference between output_threshold_pct_rise and input_threshold_pct fall. Similarly Output fall delay is time difference between output_threshold_pct_fall and input_threshold_pct_rise.

Transition time : Time it takes for a signal to changes its state from one level to another level. Transition time is represented in terms of slew in liberty. Actually slew is inversely proportional to transition time. More the transition time, lesser is the slew rate and vice-versa. As we know that

voltage transition at the output is :

V = Vdd * [ 1 - e^ ( -t/(RC ) ) ] 

As Voltage equation is exponential, the voltage waveform is asymptotic at ends It is difficult to determine the exact start and end point of transition hence transition time is defined in terms of threshold values as follow :

# lower threshold point for falling  edge

slew_lower_threshold_pct_fall  : 30;

# upper threshold point for falling  edge

slew_upper_threshold_pct_fall : 30;

# lower threshold point for rising  edge

slew_lower_threshold_pct_rise : 70;

# upper threshold point for rising  edge

slew_upper_threshold_pct_rise : 70;

Reading from a file in tcl

It is very common to read from and/or write to a file in any programming language. In tcl also, one frequently uses file operations. read command in tcl reads the entire file and stores it into a variable. One can, then, perform the desired operations onto the read data. The normal command sequence to read a file in tcl language is as below:

// script to read and display contents

set infile [open input_file.rpt r] // Create a file pointer and point it to the file to be read

set file_data [read $infile]            // Assign file_data with contents of infile

close $infile                                        // Detach the file pointer from file to be read

set lines [split $file_data “\n”]   

// Split the file contents by lines and assign each line to an element of list

foreach element $lines {

                puts $element                  // Display each element of $lines onto screen.

}

2-input AND gate using 2:1 mux

2-input AND gate implementation using 2:1 mux: Figure 1 below shows the truth table of a 2-input AND gate. If we observe carefully, OUT equals '0' when A is '0'. And OUT follows B when A is '1'. So, if we connect A to the select pin of a 2:1 mux, AND gate will be implemented if we connect D0 to '0' and D1 to 'B'.

Figure 1: Truth table of AND gate

Figure 2 below shows the implementation of 2-input AND gate using a 2:1 multiplexer.

Figure 2: Implementation of AND gate using a 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux: Figure 3 below shows the truth table of a 2-input NAND gate. If we observe carefully, OUT equals '1' when A is '0'. Similarly, when A is '1', OUT is B'. So, if we connect SEL pin of mux to A, D0 pin of mux to '1' and D1 to B', then it will act as a NAND gate.

Figure 3: Truth table of 2-input NAND gate

Figure 4 below shows the implementation of a 2-input NAND gate using 2:1 mux.

Figure 4: Implementation of 2-input NAND gate using 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input AND gate using 2:1 mux

2-input OR gate using 2:1 mux

2-input OR gate using 2x1 mux: Figure 5 below shows the truth table for a 2-input OR gate. If we observe carefully, OUT equals B when A is '0'. Similarly, OUT is '1' (or A), when A is '1'. So, we can make a 2:1 mux act like a 2-input OR gate, if we connect D0 pin to B and D1 pin to A, with select connected to A.

Figure 5: Truth table of 2-input OR gate

Figure 6 below shows the implementation of 2-input OR gate using a 2:1 multilpexer:

Figure 6: Implementation of 2-input OR gate using 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux

2-input XNOR gate using 2:1 mux

2-input XNOR gate using 2x1 mux: Figure 1 below shows the truth table of a 2-input XNOR gate. If we observe carefully, OUT equals B' when A is '0' and equals B when A is '1'. So, a 2-input XNOR gate can be implemented from a 2x1 mux, if we connect SEL pin to A, D0 to B' and D1 to B.

Figure 1: Truth table of 2-input XNOR gate

The implementation of 2-input XOR gate using a 2x1 mux is as shown in figure 2.

Figure 2: Implementation of 2-input XNOR gate using 2x1 mux

Similarly, we can observe the output for different values of B and follow the same steps to obtain the XNOR gate implementation.

8x1 multiplexer using 4x1 multiplexer

An 8x1 mux can be implemented using two 4x1 muxes and one 2x1 mux. 4 of the inputs can first be decoded using each 4-input mux using two least significant select lines (S0 and S1). The output of the two 4x1 muxes can be further multiplexed with the help of MSB of select lines at further stage. The implementation of 8x1 using 4x1 and 2x1 muxes is shown in figure 1 below:

2-input NOR gate using 2:1 mux

2-input NOR gate using 2x1 mux: Figure 1 below shows the truth table of a 2-input NOR gate. If we observe carefully, OUT equal B' when A is '0'. Similarly, OUT equals '0' when A is '1'. So, we can make a 2-input mux act like a 2-input NOR gate, if we connect SEL of mux to A, D0 to B' and D1 to '0'.

Figure 1: Truth table of 2-input NOR gate

Figure 2 shows the implementation of 2-input NOR gate using 2:1 mux.

Figure 2: Implementation of 2-input NOR gate using 2x1 mux

Similarly, we can connect B to select pin of mux and follow the same procedure of observation from truth table to get the NOR gate implemented.

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux
• 2-input AND gate using 2:1 mux