DFT basics

DFT stands for Design For Testification. DFT engineers try to make the testing of design more cost effective by introducing some structures into the design itself. By doing so, the overall test cost, and hence, cost of production comes down. Below, we list some of our posts covering the basics of DFT. Please provide your feedbacks regarding the topics you want to see as a part of this list. :-) Happy learning.

• Controllability and observability - basics of DFT

• Scan chains

• Lockup latches - basics and timing scenarios

• Lockup latches vs lockup registers - what to choose

• MBIST (Memory Built-In Self Test)

• LBIST (Logic Built-In Self Test)

Setup time vs hold time

In digital designs, each and every sequential element has some restrictions related to the data with respect to clock in the form of windows in which data can change or not. There is always a region around the active edge of the clock in which data is not allowed to change at the input of the sequential element. This is because, if the data changes at the input within this window, we cannot guarantee the output. If this happens, there can be one of the three possibilities:

• Current output data can be the result of current input data
• Current output data can be the result of previous input data
• The output can go metastable (as explained in metastability)

This region around clock edge is marked by two boundary lines, one perrtaining to setup time, and other to hold time. The region between these two lines is generally termed as setup-hold window. Figure 1 below shows the setup-hold window.

Figure 1: Figure showing setup/hold window of a sequential element

There are certain points of difference between setup time and hold time that we need to keep in mind:

• Setup time signifies the point in time before which data needs to be stable, whereas hold time is the point of time after which the data needs to be stable

• Adherence to setup time ensures that the data launched at previous active clock edge by another flip-flop gets captured at the current clock edge. On the other hand, adherence to hold time ensures that the data launched at the current edge does not get captured on the same edge.

• Above point also means that setup time adherence ensures that the design goes to next state smoothly, whereas hold time adherence means the current state is not disturbed.

Hope this post helped you in understanding the basic difference in setup time and hold time.

Also read:

• Clock latency
• False paths basics and examples
• Propagation delay in logic gates
• Integrated clock gating cell (ICG)
• Basics of latch timing