One of the most
important things in designs is to ensure glitch free propagation of clocks.
Even a single glitch in clock path can cause the chip to be metastable and even
fail. A glitch is any unwanted clock
pulse that may cause the sequential cells to consider it as an actual clock
pulse. Thus, a glitch can put your device in an unwanted state that is
functionally never possible. That is why; there should never be a glitch in
clock path. Every effort should be done by designers to minimize its
probability. The figure below shows a flip-flop receiving a data signal and a
clock signal; if there is some glitch (unwanted change of state) in clock, it
will take it as a real clock edge and latch the data to its output. However, if
the pulse is too small, the data may not propagate properly to output and the
flop may go metastable.
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| Figure showing functional glitch in clock path |
There may be following kind of
cells present in clock path:
1) Buffers/inverters: Since, there is only
one input for a buffer/inverter, the glitch may occur on the output of these
gates only through coupling with other signals in the vicinity. If we ensure
that the buffer/inverter has good drive strength and that the load and
transition at its output are under a certain limit, we can be certain that the
glitch will not occur.
2) Combinational gates: There can be
combinational gates other than buffers/inverters in clock path, say, a 2-input
AND gate having an enable signal that tells if the clock is to be propagated or
not. Each combinational gate might have one or more clocks and data/enable
pins. Let us say, we have a two input AND gate with one input as clock and the
other acting as an enable to the clock. We can have following cases possible:
i) The
other input is static: By static, we mean the other input will not change
on the fly. In other words, whenever the enable will change, the clock will be
off. So, enable will not cause the waveform at the output of the gate to
change. This case is similar to a buffer/inverter as the other input will not
cause the shape of the output pulse to change.
ii) The
other input is toggling: In this case, the enable might affect the waveform
at the output of the gate to change. To ensure that there is not glitch causes
by this, there are certain requirements related to skew between data and clock
to be met, which will be discussed later in the text. These requirements are
termed as clock gating checks.
3 3) Sequential gates: There may also be
sequential gates in clock path, say, a flop, a latch or an integrated clock
gating cell with the clock at its clock input and the enable for the clock will
be coming at its data input. The output of these cells will be a clock pulse.
For these also, two cases are possible as in case 2. In other words, if the
enable changes when clock is off, the enable is said to be static. In that
case, the output either has clock or does not have clock. On the other hand, if
the input is toggling while clock is there at the input, we may get away by
meeting the setup and hold checks for the enable signal with respect to clock
input.
As discussed above, to ensure a
glitch free propagation of clock at the output of the combinational gates, we
have to ensure some timing requirements between the enable signal and clock.
These timing requirements ensure that there is no functionally unwanted pulse
in clock path. If we ensure these timing requirements are met, there will be no
functional glitch in clock path. However, glitches due to crosstalk between
signals can still occur. There are other techniques to prevent glitches due to
crosstalk. The functional glitches in clock path can be prevented by ensuring
the above discussed timing requirements. In STA, these requirements are
enforced on designs through timing checks known as clock gating checks. By ensuring these checks are applied and taken
care of properly, an STA engineer can sign-off for functional glitches. In
later posts, we will be dealing with these checks in more details.
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