VLSI UNIVERSE

Moore's law

Moore's law
Source: Wikipedia
No comments:
Email ThisBlogThis!Share to XShare to FacebookShare to Pinterest
Labels: computer trivia, VLSI TRIVIA
Newer Posts Older Posts Home
Subscribe to: Comments (Atom)

Motivate me to write more

If you think my content has helped you achieve your goals, you can show contribution by contributing to my paypal profile.

paypal


Thanks a lot in advance. :-)

Popular Posts

  • Setup time and hold time basics
    In digital designs, each and every flip-flop has some restrictions related to the data with respect to the clock in the form of window...
  • Lockup latch – principle, application and timing
    What are lock-up latches : Lock-up latch is an important element in scan-based designs, especially for hold timing closure of shift modes....
  • Clock gating checks
    Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. ...
  • XOR/XNOR gate using 2:1 MUX
    2-input XOR gate using a 2:1 multiplexer : As we know, a 2:1 multiplexer selects between two inputs depending upon the value of its select...
  • 2x1 mux using NAND gates
    As we know, the logical equation of a 2-input mux is given as below:                       Y = (s' A   +    s B) Where s is the sele...
  • Reset Synchronizer
    Need for reset synchronizer : The way most of the designs have been modelled needs asynchronous reset assertion and synchronous de-assert...
  • Synchronizers
    Modern VLSI designs have very complex architectures and multiple clock sources. Multiple clock domains interact within the chip. Also,...
  • False paths basics and examples
    False path is a very common term used in STA. It refers to a timing path which is not required to be optimized for timing as it will never...
  • Recovery and removal checks
    Recovery and removal checks are associated with deassertion of asynchronous reset. The assertion of reset causes the output to get reset a...
  • Setup check and hold check for flop-to-latch timing paths
    In the post ( Setup and hold – basics of timinganalysis ), we introduced setup and hold timing requirements and also discussed why the...

Submit a query/feedback

Name

Email *

Message *

Blog Posts

  • MOSFET BASICS
    • post1
  • LOGIC DESIGN QUESTIONS
    • BCD multiply-by-5 circuit

Blog Archive

  • ▼  2025 (2)
    • ▼  April (1)
      • Why clock gating checks not there in shift mode
    • ►  January (1)
  • ►  2024 (1)
    • ►  November (1)
  • ►  2023 (1)
    • ►  May (1)
  • ►  2022 (3)
    • ►  December (3)
  • ►  2020 (21)
    • ►  November (1)
    • ►  August (3)
    • ►  July (2)
    • ►  June (1)
    • ►  May (3)
    • ►  April (7)
    • ►  March (3)
    • ►  February (1)
  • ►  2019 (21)
    • ►  November (2)
    • ►  October (2)
    • ►  September (2)
    • ►  July (3)
    • ►  June (3)
    • ►  May (1)
    • ►  April (1)
    • ►  March (6)
    • ►  February (1)
  • ►  2018 (7)
    • ►  December (1)
    • ►  September (1)
    • ►  August (2)
    • ►  July (1)
    • ►  May (1)
    • ►  January (1)
  • ►  2017 (43)
    • ►  December (5)
    • ►  November (4)
    • ►  October (7)
    • ►  September (1)
    • ►  August (4)
    • ►  April (2)
    • ►  March (7)
    • ►  February (6)
    • ►  January (7)
  • ►  2016 (74)
    • ►  December (16)
    • ►  November (12)
    • ►  October (10)
    • ►  September (7)
    • ►  August (4)
    • ►  July (6)
    • ►  June (6)
    • ►  May (5)
    • ►  April (8)
  • ►  2015 (31)
    • ►  September (2)
    • ►  August (2)
    • ►  June (23)
    • ►  May (1)
    • ►  April (3)
  • ►  2014 (19)
    • ►  December (4)
    • ►  November (2)
    • ►  August (3)
    • ►  July (4)
    • ►  June (1)
    • ►  May (3)
    • ►  April (1)
    • ►  January (1)
  • ►  2013 (26)
    • ►  October (1)
    • ►  September (5)
    • ►  August (4)
    • ►  July (5)
    • ►  June (2)
    • ►  May (6)
    • ►  March (1)
    • ►  February (1)
    • ►  January (1)
  • ►  2012 (1)
    • ►  December (1)

Categories

[accordion] [item title="Title Of Tab 1"] INSERT CONTENT HERE [/item] [item title="Title Of Tab 2"] INSERT CONTENT HERE [/item] [item title="Title Of Tab 3"] INSERT CONTENT HERE [/item] [/accordion]

TOP SITES

VLSI Logic Design Interview Questions
** VLSI WORLD
Software in layman language
Protected by Copyscape

Translate

Total Pageviews
My sitemap
Powered by Blogger.