Which type of jitter matters for timing slack calculation?

In the post Clock jitter, we learnt about the basics of clock jitter. We also learned about different types of clock jitter. Now, the question arises as to what type of clock jitter is useful for calculation of timing slack, both setup and hold slacks. We will gradually try to build understanding for the same.

If we look into the equation of setup slack for a positive edge-triggered flip-flop to another positive edge-triggered flip-flop, we see that setup slack depends upon "clock period". Now, if look closely, we will find that the clock period that we are talking about is actually distance between two clock edges. The larger the distance between the clock edges, greater will be the clock period. Hence, more positive will be setup slack.

 Now, period jitter represents the absolute deviation of clock period from its ideal clock period. So, the jitter we should be looking for is maximum value of "peak-to-peak period jitter". Peak-to-peak period jitter can either increase or decrease clock period. But, we need to take the effect of jitter to decrease clock period. This is because we have to take the worst case of clock period to have most pessimistic setup slack value. And the worst clock period will occur when peak-to-peak jitter is maximum.

So, we can say that for setup slack calculation,

Clock period (actual) = Clock period (ideal) - peak-to-peak jitter (maximum)

What will happen to clock jitter if I divide down the clock?

As we have discussed above, due to clock jitter, for setup calculation, we will assume that peak-to-peak period jitter has caused edge 2 to come closer to edge 1, thereby reducing actual clock period by that margin. Similarly, edge 3 can come closer to edge 2. So, ideally, if we look at DIV_2 clock, the possible jitter here should be 2 times the jitter of SOURCE_CLOCK. Similarly, a DIV_4 clock is expected to have 4 times the jitter and a DIV_8 clock is expected to have 8 times the jitter. And so on..

Now comes the tricky part. As per the definition of long term jitter, nth edge of clock cannot have a jitter more than long term jitter. So, if I say that a PLL has a long term jitter spec of 6 times that of maximum peak-to-peak period jitter, then a DIV_8 clock will have peak-to-peak jitter equal to 6 times the peak-to-peak period jitter of SOURCE_CLOCK. Even a DIV_16 clock will have same maximum jitter.


What will happen to clock jitter for a multicycle path?
Similar to the case of divided down version of clock, a multicycle path also involves other than consecutive edges. So, similar concepts will apply here. So, a multicycle path for setup of 2 will have a jitter of 2 times the peak-to-peak jitter of SOURCE_CLOCK, etc.

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Clock jitter

Clock jitter: By definition, clock jitter is the deviation of a clock edge from its ideal position in time. Simply speaking, it is the inability of a clock source to produce a clock with clean edges. As the clock edge can arrive within a range, the difference between two successive clock edges will determine the instantaneous period for that cycle. So, clock jitter is of importance while talking about timing analysis. There are many causes of jitter including PLL loop noise, power supply ripples, thermal noise, crosstalk between signals etc. Let us elaborate the concept of clock jitter with the help of an example:

A clock source (say PLL) is supposed to provide a clock of frequency 10 MHz, amounting to a clock period of 100 ns. If it was an ideal clock source, the successive rising edges would come at 0 ns, 100 ns, 200 ns, 300 ns and so on. However, since, the PLL is a non-ideal clock source, it will have some uncertainty in producing edges. It may produce edges at 0 ns, 99.9 ns, 201 ns etc. Or we can say that the clock edge may come at any time between (<ideal_time>+- jitter); i.e. 0, between 99-101 ns, between 199-201 ns etc (1 ns is jitter). However, counting over a number of cycles, average period will come out to be ~100 ns.

Figure 1 below shows the generic diagram for clock jitter:

Please note that the uncertainty in clock edge can be for both positive as well as negative edges (above example showed only for positive edges). So, there are both full cycle and half cycle jitters. By convention, clock jitter implies full cycle clock jitter.


Types of clock jitter: Clock jitter can be measured in many forms depending upon the type of application. Clock jitter can be categorized into cycle-to-cycle, period jitter and long term jitter.

• Cycle to cycle jitter: By definition, cycle-to-cycle jitter signifies the change in clock period accross two consecutive cycles. For instance, it will be difference in periods for 1st and 2nd cycles, difference in periods for 10th and 11th cycles etc. It has nothing to do with frequency variation over time. For instance, in figure below, the clock has drifted in frequency (from period = 10 ns to period = 1 ns), still maintaining a cycle-to-cycle jitter of 0.1 ns. In other words, if t2 and t1 are successive clock periods, then cycle_to_cycle_jitter = (t2 - t1).

• Period jitter: It is defined as the "deviation of any clock period with respect to its mean period". In other words, it is the difference between the ideal clock period and the actual clock period. Period jitter can be specified as either RMS period jitter or peak-to-peak period jitter.
• Peak-to-peak period jitter: It is defined as the jitter value measuring the difference between two consecutive edges of clock. For instance, if the ideal period of the clock was 20 ns, then for clock shown above,
• for first cycle, peak-to-peak period jitter = (20 - 20) = 0 ns
• for second cycle, peak-to-peak period jitter = (20 - 19.9) = 0.1 ns
• for last cyle, peak-to-peak period jitter = (20 - 1) = 19 ns
• RMS period jitter: RMS period jitter is simply the root-mean-square of all the peak-to-peak period jitters available.

• Long term jitter: Long term jitter is the deviation of the clock edge from its ideal position. For instance, for a clock with period 20 ns, ideally, clock edges should arrive at 20 ns, 40 ns and so on. So, if 10th edge comes at 201 ns, we will say that the long term jitter for 10th edge is 1 ns. Similarly, 1000th edge will have a long term jitter of 0.5 ns if it arrives at 20000.5 ns.

Let us try to understand the difference between all the three kinds of jitter with the help of an illustrative example waveform below:

Reference:
* Understanding SYSCLK jitter

Also read:

• Interview questions related to clock jitter and duty cycle variations

Post your query

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Can jitter in clock effect setup and hold violations?

First of all, we need to understand what is meant by jitter. In most simplistic language, jitter is the uncertainty of a clock source in production of clock edges. For example, if we say that there is a 100 MHz clock source. Ideally, it should produce a clock edge at 0 ns, 10 ns, 20 ns... So, if we say that there was a clock edge at time t = 30 ns, we should get the next clock edge at t = 40 ns. But this is hardly so; due to the uncertainty of getting a clock edge, we might get the next edge between 39.9 ns to 40.1 ns. So, we say that 0.1 ns is the jitter in the period of the clock. In reality, the definition of jitter is more complex. But, for our scope, this understanding is sufficient.

Let us consider a simple timing path from a positive edge-triggered flip-flop to a positive edge-triggered flip-flop.

Now, let us come to our discussion. First, let us discuss the effect of clock jitter on setup slack.

Effect of clock jitter on setup slack for single cycle paths: From our knowledge of STA basics, setup check formed, in this case, will be from edge 1 -> edge 3. Now, if we know that edge 1 arrived at 20 ns, then edge 3 may arrive at any time (20 ns + CLOCK_PERIOD + jitter) and (20 ns + CLOCK_PERIOD - jitter). So, to cover worst case timing scenario, we need to time as per (20 ns + CLOCK_PERIOD - jitter). So, effectively, we will get (CLOCK_PERIOD - jitter) as effective clock period.

In other words, jitter in clock period makes the setup timing more tight. Or it decreases setup slack for single cycle timing paths.


Effect of clock jitter on hold slack for single cycle paths: Going on the same grounds as setup slack, hold check will be from edge 1 -> edge 1 only. And we know with certainty that edge 1 will leave the source at 20 ns only. So, hold slack should not get bothered by the amount of jitter present at the clock source for single cycle timing paths.

Now, you understand the basics of  how jitter affects setup and hold slacks. We can state as below:

If the check being formed involves two different edges of same polarity (for instance, different rising edges), then, jitter in clock period will affect setup slack. Otherwise, it will not.

Now, can you guess the effect of jitter on setup and hold slacks for zero cycle timing paths?

Also, what will be the amount of pessimism needed to be taken into account for setup and hold slacks' calculations if the timing path is a multi-cycle path taking 2 cycles for setup and zero cycle for hold?

Also read:

• Interview questions related to clock jitter and duty cycle variations