Is hold always checked on the same edge?

One of the guys asked me a question, "Why is hold always checked on the same edge?" Normally, it is taught in books/colleges that hold is frequency independent because it is checked on same edge. But, is it really true? It is true only for some of the many cases. Hold can be checked on the same edge, next edge or previous edge depending upon the scenario. In this post, we will discuss those cases one by one, and try to generalize if this statement holds true.

How to determine the edge on which hold check needs to be checked: For most of us, it seems quite confusing to arrive at the conclusion of how to determine the hold edge. Let us try to use a state machine perspective here. In state machine theory, we study that synchronous digital circuits can be considered as state machines moving from one state to another. This state transition happens on each clock edge as shown in figure 1 below.

Figure 1: Each clock edge corresponds to a design state

If we look at each flip-flop, every positive edge-triggered flip-flop changes its state at positive clock edge and all negative edge-triggered flip-flops transition state at negative clock edge. Similarly, all negative edge-triggered flip-flops transition state at negative clock edge as shown in figure 2 below.

Figure 2: State transition for positive edge-triggered and negative edge-triggered flip-flops

Or, we can represent the states of positive edge-triggered and negative edge-triggered flops as separate as shown in figure 3 below.

Figure 3: States of positive and negative edge-triggered flops represented symbolically

Let us have a scenario of a timing path from a positive edge-triggered flop to a positive edge-triggered flop. In the figure 4 below, flip-flop "2" transitions to state (K+1) depending upon the value of flip-flop "1" at state (K).

Figure 4: A sample timing path from positive edge-triggered flip-flop to positive edge-triggered flip-flop

Here, the data launched from ff1 should help ff2 transition to state "K+1", meaning, it should be captured at the corresponding clock edge. This represents setup check. Also, it should not disturb state "K" of ff2, meaning it should not get captured at this edge. This represents hold check. So, in this case hold check is on the same edge as the present state of start and end flops is the same edge.

Figure 5: Setup and hold checks for positive-to-positive edge-triggered timing paths

Now, let us take a look on the scenario where-in hold check is not on the same edge. Let us take a timing path launching data from negative edge and capturing at positive edge. This scenario is shown in figure 6 below.

Figure 6: Timing path from negative-to-positive edge-triggered flop

Here, positive edge-triggered flip-flop transitions states on positive edge and negative edge-triggered flop transitions on negative edges. So, the data launched from negative edge-triggered flop corresponding to state "X" should get captured on positive edge-triggered flop on state "Y+1", which corresponds to setup check. And it should not get captured on state "Y", which corresponds to hold check.

Thus, we have looked upon different cases of hold capturing edge being same or different than the launch edge. For all the possible cases of setup and hold checks, you can follow below posts:

• Setup and hold checks
• Setup checks and hold checks for register to register timing paths
• Setup checks and hold checks for register-to-latch timing paths
• Setup checks and hold checks for latch-to-reg timing paths
• Can hold check be frequency dependant

Design puzzle : 2-input mux glitch issue

Problem statement: A 2-input multiplexer has both of its inputs getting value of "1". Will there be any toggle (glitch) happening at the output of the multiplexer? If yes, is that expected? What if both the inputs are getting value of "0"?

Answer: 

We all know that a multiplexer's output is equal to

IN0 if SEL = 0

IN1 if SEL =1

So, if both IN0 and IN1 are getting same logic value, output must not toggle. However, if we observe carefully, there is a high chance of a momentary glitch at the output in case both inputs are at value "1" and select toggles from "1" to "0". To understand this, we need to look into the internal structure of the mux, which is as shown in figure 2 below.

The figure says that output goes momentarily to "0" before finally settling down to "1". Why is this so? The reason behind this is the two paths going from SEL to OUT and toggling of both the inputs of final OR gate. And there is asymmetry of delays with one inverter being extra in one of the paths. This causes the output of the mux to go momentarily to zero.

Let us analyze this with the help of timing waveforms (assuming delay of each element to be 1 unit):

Thus, it is clear from the timing waveforms that there is a glitch in the output. It is possible to minimize the extent of this glitch by minimizing the difference of delays between the two paths getting formed between the SEL and OUT. However, it cannot be guaranteed even with greatest of precision during design as there are mismatches in fabrication of individual gates. So, even the best of multiplexers will have this limitation, however small it may be, unless designed specifically for this purpose. Can you suggest a design improvement that can help in this scenario?

One is forced to think here that what can be the consequences of such a glitch and what remedies can be there for this. I had written a post Glitches in combinational circuits that discussed what can be the consequences of glitches in combinational circuits. This scenario is a special case, but with some twist. Let us discuss all the cases one by one.

• If this case is in a data path for synchronous circuits, there is no issue as discussed in one of the points in our post Glitches in combinational circuits.
• If this case happens for a data path in asynchronous circuits, this can be an issue. So, synchronization circuits have to be designed with utmost care and following the rules of data synchronization
• If this scenario occurs in either path of clock or reset, this is an issue as this glitch can alter the state of the design by either letting the flop capture data at "D" pin by acting as an extra clock pulse, or can reset the flop.