: VLSI n EDA

When electron beam hits phosphorus coated screen, some of the energy of these electrons in dissipated as heat and rest is transferred to electrons of phosphorus which makes them jump to higher energy levels. As we know that higher energy state is unstable and when electron comes to its original state energy is emitted in the form of light(color of light depend upon level from which electrons is returning).

In Ph, some energy levels are less stable than others so electrons in this state returns more rapidly than others.

Hence energy(in the form of light) emitted when these unstable electron return from higher state to its original state while electrons are bombarded on it is called fluorescence.

While the energy emitted when stable electrons return from higher energy levels to its original energy level once electron beam excitation is removed is called phosphorescence.

most of the light emitted in typical Ph is phosphorescence.

Persistence : It is defined as the time from removal of excitation of electron beam to the time when the phosphorescence has decayed to 10% of initial light output. Typically it is between 10-60 microsecond.

In the post setup and hold time violations, we learnt about the setup time violations and hold time violations. In this post, we will learn the approaches to tackle hold time violations. Following strategies can be useful in reducing the magnitude of hold violation and bringing the hold slack towards a positive value:

1. Insert delay elements: This is the simplest we can do, if we are to decrease the magnitude of a hold time violation. The increase in data path delay can be increased if we insert delay elements in the data-path. Thus, the hold violating path's delay can be increased, and hence, slack can be made positive by inserting buffers in hold violating data-path.

2. Reduce the drive strength of data-path logic gates: Replacing a cell with a similar cell of less drive strength will certainly add delay to data-path. However, there is a slight chance of decrease in data-path delay if the cell load is dominated by intrinsic capacitance as we discussed in how delay of a standard cell changes with drive strength

3. Use data-path cells with higher threshold voltages: If you have multiple flavors of threshold voltages in your design, the cells with higher threshold voltage will certainly have higher delays. So, this must be the first option you must be looking for to resolve hold violations.

4. Improve hold time of capturing flip-flop: Using a capturing flip-flop with higher drive strength and/or lower threshold voltage will give a lower hold time requirement. Also, improving the transition at flip-flop's clock pin reduces its hold time requirement.

5. Detoured routing: Detoured routing can be adoped as an alternative to insertion of delay elements as it will add load to the driving cell as well as provide additional net delay thereby increasing the data-path delay.

6. Play with clock skew: A positive skew degrades hold timing and a negative skew aids hold timing. So, if a data-path is violating, we can either decrease the latency of capturing flip-flop or increase the clock latency of launching flip-flop. However, in doing so, we need to keep in mind the setup and hold slacks of other timing paths starting and/or ending at these flip-flops.

7. Increase the clk->q delay of launching flip-flop: A launching flip-flop with more clk->q delay will help ease the hold timing of the data-path. For this, either we can decrease the drive strength of the flip-flop or move it to higher threshold voltage.

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