Engineering Change Order (ECO)

A semiconductor chip undergoes synthesis, placement, clock tree synthesis and routing processes before going for fabrication. All these processes require some time, hence, it requires time (9 months to 1 year for a normal sized chip) for a new chip to be sent for fabrication. As a result of cut-throat competition, all the semiconductor companies stress on Cycle-time reduction to be ahead of others in the race. New ways are being found out to achieve the same. New techniques are being developed and more advanced tools are being used. Sometimes, the new chip to be produced may be an incremental change over an existing product. In such a case, there may not be the need to go over the same cycle of complete synthesis, placement and routing. However, everything may be carried out in incremental manner so as to reduce engineering costs, time and manufacture costs.

It is a known fact that the fabrication process of a VLSI chip involves manufacture of a number of masks, each mask corresponding to one layer. There are two kinds of layers – base and metal. Base layers contain the information regarding the geometry and kind of transistors, resistors, capacitors and other devices. Metal layers contain information regarding metal interconnects used for connection of devices. For a sub-micron technology, the mask costs may be greater than a million dollars. Hence, to minimize the cost, the tendency is to reuse as many masks as possible. So, it is tried to implement the ECO with minimal number of layers change. Also, due to cycle time crunch, it is a tradition to send the base layers for the manufacture of masks while the metals are still modified to eliminate any kind of DRC’s. This saves around two weeks in cycle time. The base layer masks are developed while metal layers are still being modified.

What conditions cause an Engineering Change Order: As mentioned above, ECO are needed when the process steps are needed to be executed in an incremental manner. This may be due to-

• Some functionality enhancement of the existing device. This functionality enhancement change may be too small to undergo all the process steps again
• There may be some design bug that needs to be fixed and was caught very late in the design cycle. It is very costly to re-run all the process cycle steps for each bug in terms of time and cost. Hence, these changes need to be taken incrementally.

Normally, there is a case that design enhancements/functional bug fixes are being implemented after the design has already been sent for fabrication. For instance, the functional bug may be caught in silicon itself.  To fix the bug, it is not practical to restart the cycle.

The ECO process starts with the changes in the definition to be implemented into the RTL. The resulting netlist synthesized from the modified netlist is, then, compared with the golden netlist being implemented. The logic causing the difference is then implemented into the main netlist. The netlist, then, undergoes placement of the incremental logic, clock tree modifications and routing optimizations based upon the requirements.

Kinds of ECO: The engineering change orders can be classified into two categories:

• All layers ECO: In this, the design change is implemented using all layers. This kind of ECO provides advantage in terms of cycle time and engineering costs. It is implemented whenever the change is not possible to be carried out without all layer change e.g. there is an updation in a hard macro cell or the change may require updation of 100’s of cells. It is almost impossible to contain such a large change to a few layers only.
• Metal-only ECO: As discussed above, due to incurring costs, sometimes, it may not be practical to use all the layers (base + metal) to do the ECO. In that case, to minimize the cost, it is required to be completed with changes only in minimal number of metal layers. These days, it is expected that every design will be re-opened for the ECOs. So, an adequate number of spare cells are sprinkled during the implementation all over the design to be used later on. These cells are spread uniformly over the design. The inputs of these cells are tied. Whenever the need for an ECO arises, the cells to be implemented can be mapped into the existing spare cells. Hence, there is no need to change the base layers in such a case. Only the connections need to be updated which can be done by changing the metal layers only. Hence, the base layer cost is saved.

Steps to carry out an ECO: The ECOs are best implemented manually. There exist some automated ways to carry out the functional ECOs, but the most efficient and effective method is to implement manually. Generally, following steps are employed to carry out Engineering Change Orders:

1. The RTL with ECO implemented is synthesized and compared with the golden netlist.
2. The delta is implemented into the golden netlist. The modified netlist is then again compared with the synthesized netlist to ensure the logic has been implemented correctly.
3. The logic is the placed incrementally. However, if it is metal-only ECO, spare cells in the proximity of the changed logic are found out.
4. The connections are, then, modified in metal layers.

Related posts:

• Metal ECO - the process
• Spare cells
• Timing arcs
• Setup and hold - basics of timing analysis
• Interesting design problem - BCD multiply by 5 circuit

MBIST (Memory Built-In Self Test)

The ever increasing size and number of memories in the Systems on Chip has presented the designers and test engineers with a challenge for huge number of functional or ATPG patterns for verification of memory functionality. So, to test the memory functionality either functionally or through ATPG requires huge test time, and hence, huge test cost. It is almost impossible in such scenario to verify memory functionality fully. Thus, the designers are left with only one way; i.e. to verify memory functionality through BIST (Built-In Self Test) functionality.

BIST is an inbuilt testing circuitry within a software/hardware module. We just need to trigger the circuitry from outside. This circuitry, then, runs the inbuilt patterns/algorithms and returns if the module is working properly. This, being inbuilt does not need to be supplied with patterns from outside. Also, since, this is within a module, hence, we can take the modular approach for testing which reduces run time significantly.

The built-in self test employed for memories is known as MBIST (Memory Built-In Self Test). Like other BIST logic, MBIST logic is inbuilt within memory only. The MBIST logic may be capable of running several algorithms to verify memory functionality and test for memory faults specifically designed and optimized for these.

There is usually a wrapper around memory, known as ‘memory collar’ that is used to select between functional inputs and test inputs based upon MBIST/functional mode selection bit. It interfaces the memory with on-chip logic and MBIST controller. The MBIST controller indicates the start of MBIST with a select input. The memory, then, starts the BIST algorithms and provides the test output to the controller. The controller compares this output with the reference output and indicates if the MBIST has passed or failed. There can be one controller for several memories. Also, memories can share the collar depending upon the test time requirement and type of memories.

Advantages of MBIST: There are several advantages of MBIST insertion over functional/atspeed testing such as:

• It allows for robust testing of memories 
•  Reduced test time 
•  All the memories of the design can be tested in parallel 
•  Lesser test cost

Disadvantages of MBIST: Inspite of many advantage of MBIST, there is only one remarkable limitation. Insertion of MBIST causes increase in area. However, this increase in area is very small in comparison to the benefits it provides.

Related posts:

• Lockup latches - soul mate of scan based designs
• Scan chains - the backbone of DFT
• LBIST
• Controllability and observability - basics of DFT
• Lockup latches vs lockup registers - what to choose