First of all, we need to understand the basics of scan timing. A usual scan cycle looks pretty much like the one below. Tester sends shift data once every one cycle, and that usually is during clock low pulse. Image1 below shows typical scanin assertion and scanout observation during shift cycles. Here, I am showing both to be different, but usually they are done concurrently. during the same shift cycle, know obviously to save test time. Thus, every scan cycle consists of a positive and a negative edge.
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| Image1: Shiftin and shiftout cycles |
Now, imagine a positive-edge triggered flop feeding to a negative edge-triggered flop. At the end of every scan cycle, both the flops will hold same data. Thus, the tester will not be able to provide "10" or "01" pattern on this pair. This may or may not result in a coverage drop, but it would result in a manual review of the logic to make sure there isnt any.
Similarly, during observation through scan out, tester will never be able to observe data on the output of negative edge flop, because of the redundancy of the data, resulting again in coverage drop.
Thus, the efforts are there to not have any such scenario in the first place during scan stitching. But if there are, a dummy scan element (or lockup latch) is put in place to elongate the data for one cycle. We need to note that doing this increases the scan chain length by 1, which is in contrary to other lockup latch cases. That is why, we are calling this as a dummy scan element.
Thus, now we know, why a positive edge triggered flop followed by a negative edge triggered flop needs a lockup element. Feel free to comment in case of any queries/feedbacks.