Clock gating timing paths

A timing path falls under the category of clock gating timing paths, when:

1. The endpoint is the "EN" pin of Integrated Clock Gating (ICG) cell   OR
2. The endpoint is one of the input pins of a combinational cells with at least one of the other pins getting a clock signal

The motive behind a clock gating timing path being treated as a constrained path is to constrain the path in such a way that there is no glitch or metastability observed at the output of the gate. In other words, either the output of the gate transmits complete pulses of clock; or it does not transmit any signal at all. The max and min checks in case of clock gating paths are called as "clock gating setup check" and "clock gating hold checks". The startpoint for these paths can be any of input port or a sequential element. Figure 1 below shows a few examples of clock gating timing paths.

Constraining clock gating check timing paths: As explained in clock gating checks, there are two types of clock gating checks - one which require data at the endpoint to change when clock is low (AND-type check) and vice-versa (OR-type check). There are scenarios when STA tool is able to recognize the type of check being formed. This happens when the endpoint is a simple gate such as AND or OR gate. In that case, by default, these are constrained as clock gating endpoints. The only thing we have to do is to ensure that proper clock signals reach the startpoint and the endpoint. But there are scenarios when the gate is complex and it is not possible for STA tool to differentiate which of the two types of checks should be formed. In those cases, these are not by-default constrained. And we have to specifically ask the STA tool to treat these as clock gating endpoints by using "set_clock_gating_check" SDC command, in addition to defining proper clocks.