Why there needs to be a lockup latch inserted because of DFT architecture reasons

In the post lockup latches, we mentioned that it may not be advisable/allowed to have a positive edge triggered flop flop followed by a negative edge-triggered flip-flops in scan chains because of DFT specific reasons. In this post, we will try to undertstand the underlying reason.

First of all, we need to understand the basics of scan timing. A usual scan cycle looks pretty much like the one below. Tester sends shift data once every one cycle, and that usually is during clock low pulse. Image1 below shows typical scanin assertion and scanout observation during shift cycles. Here, I am showing both to be different, but usually they are done concurrently. during the same shift cycle, know obviously to save test time. Thus, every scan cycle consists of a positive and a negative edge.

Image1: Shiftin and shiftout cycles

Now, imagine a positive-edge triggered flop feeding to a negative edge-triggered flop. At the end of every scan cycle, both the flops will hold same data. Thus, the tester will not be able to provide "10" or "01" pattern on this pair. This may or may not result in a coverage drop, but it would result in a manual review of the logic to make sure there isnt any.

Similarly, during observation through scan out, tester will never be able to observe data on the output of negative edge flop, because of the redundancy of the data, resulting again in coverage drop.

Thus, the efforts are there to not have any such scenario in the first place during scan stitching. But if there are, a dummy scan element (or lockup latch) is put in place to elongate the data for one cycle. We need to note that doing this increases the scan chain length by 1, which is in contrary to other lockup latch cases. That is why, we are calling this as a dummy scan element.

Thus, now we know, why a positive edge triggered flop followed by a negative edge triggered flop needs a lockup element. Feel free to comment in case of any queries/feedbacks.

Why NMOS leads to a strong 0 and a weak 1

We frequently hear that an NMOS can pass a strong "0" and only a weak "1". Similarly, a PMOS can only pass a weak "1". But very few people actually know the reason behind this. In this post, we will delve into the details of why NMOS cannot pass a strong "1" and vice-versa.

To understand this, we have to dig deep into the behavior of MOS transistors.

Figure 1: Basic MOS structure (NMOS)

Figure 1 shows the basic structure of MOS transistor. As we know, the existence of channel (charges) is essential for it to conduct electric current. We have read that channel would exist if (Vgs > Vth), where Vth is threshold voltage of the MOSFET. This is true in case there is no electric current flowing through the channel (Drain being not connected to any voltage).

However, there is a slight correction needed to this understanding, in case there is a current flowing from Source to Drain (or vice-versa). As we know that the channel is a separation between Source and Drain terminals. And naturally, it would have some resistance (for our purpose, it wont matter if the resistance is high or low). And current flowing through a resistance naturally will have some voltage drop across it. The same is shown in figure 2 below.

Figure 2: NMOS channel as a resistor

Now, we know that the voltage level at every point in the channel will not be the same, if MOS is conducting electric current. This leads us to expand to already developed understanding. We can not talk about the entire channel, we have to talk of a point "p" in the channel. We can now say that the presence of charges at point "p" will be governed by the potential "Vgp", which is the voltage difference between Gate and point "p". Thus, for the conduction to happen, there needs to be a charge at every point in the channel.

Figure 3: Charges in NMOS with current flowing

Since, we have discussed about the principle, we can now go on to discuss about the specific use-case here. We want the NMOS to transmit a "logic 1" signal, which mean Vs = Vg. And Drain is connected through either a capacitance of a resistance to ground, completing a circuit with Source terminal. Let us assume it to be a resistance for simplicity. Initially, since Vs = Vg, it means that Vgs = 0. Hence, there is no channel in the region closer to Source terminal.

This would mean no current should flow, meaning that Vd would be 0V. And channel would exist near Drain region for sure.

Now, there exist a potential difference between Source and Drain terminals, which would cause a current to flow between these through an infinitesimal layer of charges being developed in the channel near source terminal. The exact situation would be something similar to figure 4 below. The infinitesimal layer of charges would extend to a distance which would cause a potential difference of Vth in the channel. And triangular charge distribution signifies different potential of each point in the channel as well. The greater potential difference with respect to gate, more is the amount of charge present at that point.

Figure 4: Channel formation in NMOS in saturation region

The limit of this behavior would be reached when Drain reaches a potential (Vg - Vth), thereby entire channel being infinitesimal. Upon trying to further raising voltage above this point, both drain and source would be cut-off. And further raising of voltage of Drain terminal beyond this point wont be possible. Thus, the maximum voltage the drain terminal can reach is Vs - Vth. In other words, a NMOS can never transmit an ideal "1". On similar terms, a PMOS wont be able to transmit an ideal "0" as well.

I hope this post was useful to you. Please let us know in comments your views on this.