Why NMOS leads to a strong 0 and a weak 1

We frequently hear that an NMOS can pass a strong "0" and only a weak "1". Similarly, a PMOS can only pass a weak "1". But very few people actually know the reason behind this. In this post, we will delve into the details of why NMOS cannot pass a strong "1" and vice-versa.

To understand this, we have to dig deep into the behavior of MOS transistors.

Figure 1: Basic MOS structure (NMOS)

Figure 1 shows the basic structure of MOS transistor. As we know, the existence of channel (charges) is essential for it to conduct electric current. We have read that channel would exist if (Vgs > Vth), where Vth is threshold voltage of the MOSFET. This is true in case there is no electric current flowing through the channel (Drain being not connected to any voltage).

However, there is a slight correction needed to this understanding, in case there is a current flowing from Source to Drain (or vice-versa). As we know that the channel is a separation between Source and Drain terminals. And naturally, it would have some resistance (for our purpose, it wont matter if the resistance is high or low). And current flowing through a resistance naturally will have some voltage drop across it. The same is shown in figure 2 below.

Figure 2: NMOS channel as a resistor

Now, we know that the voltage level at every point in the channel will not be the same, if MOS is conducting electric current. This leads us to expand to already developed understanding. We can not talk about the entire channel, we have to talk of a point "p" in the channel. We can now say that the presence of charges at point "p" will be governed by the potential "Vgp", which is the voltage difference between Gate and point "p". Thus, for the conduction to happen, there needs to be a charge at every point in the channel.

Figure 3: Charges in NMOS with current flowing

Since, we have discussed about the principle, we can now go on to discuss about the specific use-case here. We want the NMOS to transmit a "logic 1" signal, which mean Vs = Vg. And Drain is connected through either a capacitance of a resistance to ground, completing a circuit with Source terminal. Let us assume it to be a resistance for simplicity. Initially, since Vs = Vg, it means that Vgs = 0. Hence, there is no channel in the region closer to Source terminal.

This would mean no current should flow, meaning that Vd would be 0V. And channel would exist near Drain region for sure.

Now, there exist a potential difference between Source and Drain terminals, which would cause a current to flow between these through an infinitesimal layer of charges being developed in the channel near source terminal. The exact situation would be something similar to figure 4 below. The infinitesimal layer of charges would extend to a distance which would cause a potential difference of Vth in the channel. And triangular charge distribution signifies different potential of each point in the channel as well. The greater potential difference with respect to gate, more is the amount of charge present at that point.

Figure 4: Channel formation in NMOS in saturation region

The limit of this behavior would be reached when Drain reaches a potential (Vg - Vth), thereby entire channel being infinitesimal. Upon trying to further raising voltage above this point, both drain and source would be cut-off. And further raising of voltage of Drain terminal beyond this point wont be possible. Thus, the maximum voltage the drain terminal can reach is Vs - Vth. In other words, a NMOS can never transmit an ideal "1". On similar terms, a PMOS wont be able to transmit an ideal "0" as well.

I hope this post was useful to you. Please let us know in comments your views on this.

Does inserting lockup latch affect Logic Equivalence Check (LEC)

 Logic equivalence check is normally carried out to ensure some processing of the design (example logic synthesis) has not resulted in change of functionality. It flags any logical changes with respect to a golden set of collaterals. There are many applications of logic equivalence checking, some of the prevalent ones pertaining to:

1. Logic equivalence check between RTL and corresponding synthesized netlist to ensure the logic synthesis has not introduced any functional issues

2. Logic equivalence check between two sets of netlists after doing netlist edits. 

One thing to note here is that since RTL is the starting point here, LEC is done only for the logic present in the RTL, even for netlist vs netlist LEC (exceptions can be there). Other logic, such as scan chains are bypassed by application of certain constraints during LEC. For such logic, there are other methods to ensure correctness, such as scan tracing check to ensure there are no unintentional issues to trace scan chains.

Insertion of lockup latch also falls under non-functional netlist edits, hence not covered under LEC in normal scenarios. We must observe that fanout if lockup latch goes to scan_in pin of flop, which is not checked under LEC.