Minimum pulse width violation example

STA problem: Consider below figure, wherein minimum pulse width requirement of a flip-flop is 590 ps. It is getting clocked by a PLL of 500 MHz with a duty cycle variation of 60 ps. There are 30 buffers in clock path, each having a rise delay of 60 ps and fall delay of 48 ps. Will this setup be able to meet the duty cycle requirement of flip-flop? Find the slack available.

Solution:

Here, we must remember that pulse can be either high pulse or low pulse. So, we need to check for both. Let us start with high pulse:

Pulse width check for high pulse: Here, we are left with calculating the latest possible arrival of rising edge and earliest possible arrival of falling edge at the flip-flop. It is given that

Ideal clock period = 2000 ps (500 MHz frequency)
Ideal half cycle = 1000 ps
Duty cycle variation of clock source = 60 ps
So, if we assume that positive edge of the clock has arrived at 0 time, negative edge can arrive at any time between 940 ps (1000 - 60) and 1060 ps (1000 + 60). Taking the pessimistic case, we have to assume negative edge arrives at 940 ps thereby making the high pulse as 940 ps at clock source.

Now, there are 30 buffers with rise delay of 60 ps and fall delay of 48 ps.

Rising edge will reach flip-flop at time (0 + 30 * 60) = 1800 ps.
Falling edge will reach flip-flop at time (940 + 30 * 48) = 2380 ps
Effective pulse width visible at flip-flop = 2380 - 1800 = 580 ps

Now, the pulse width requirement = 590 ps
Slack = Actual pulse width = Required minimum pulse width = -10 ps

So, we are violating the minimum high pulse width requirement by 10 ps.

Pulse width requirement for low pulse: Similar to the earlier case, we have to find the difference in arrival of latest negative edge and earliest positive edge.

Ideal clock period = 2000 ps (500 MHz)
Ideal half cycle = 1000 ps
Duty cycle variation of clock source = 60 ps
If we assume that negative edge arrived at 0 ps, positive edge can arrive at any time between 940 ps and 1060 ps. Taking the pessimistic case, low pulse width = 940 ps at clock source.

Now, there are 30 buffers with rise delay of 60 ps and fall delay of 48 ps.

Falling edge will reach flip-flop at time (0 + 30 * 48) = 1440 ps
Rising edge will reach flip-flop at time (940 + 60 * 30) = 2740 ps
Effective pulse width visible at flip-flop = 2740 - 1440 = 1300 ps

Pulse width requirement = 590 ps
Slack = 1300 - 590 = 710 ps

So, we are meeting the low pulse width requirement by 710 ps.

Glitches in combinational circuits

What is a glitch: As per definition, a glitch is any unwanted pulse at the output of a combinational gate. In other words, a glitch is a small spike that happens at the output of a gate. A glitch happens generally, if the delays to the combinational gate output are not balanced. For instance, consider an AND gate with one of its inputs getting inverted and delayed version of  its other input. It, then will produce a short pulse (or glitch) at the ouput whenever its input goes from zero to one.

As also said above, this is due to the fact that the delays to the AND gate through two paths are not balanced. Let us elaborate with the help of below waveform. When input goes from zero to one, the other input will go to zero after some time as there is a delay equal to that of an inverter. Due to this, there will be a glitch at the output of AND gate. It needs to be noted that lesser the delay difference between the two inputs at the input of AND gate, lower will be the duration of glitch.

How are glitches harmful? Glitches may be harmful in two ways:

• Timing/functional issue: A glitch can be an issue if it propagates to the resultant logic or gets captured by a flip-flop. There can be two cases here:

• Synchronous timing paths: These are timing paths wherein we are required to meet setup and hold timings. So, even if there is a glitch, it will be within the limits of minimum and maximum delays permissible from one flip-flop to another. So, there will be no timing issue provided that you have taken care of setup and hold timings.

• Asynchronous timing paths: If the launch and capture clocks do not have any relationship, setup and hold cannot be ensured. So, if there is a glitch in the data path, it can get captured, hence, can cause issue. To prevent this, synchronizers are used and there are certain rules to be followed for asynchronous paths. These are to be followed to ensure that no wrong data gets captured due to clock glitches. It should be better to call this as functional issue as it can be taken care of only architecturally.

• High power!!! Every toggling causes power dissipation due to charging and discharging of gate capacitance. So, a glitch causes power dissipation. Even if there is no timing/functional issue associated with the glitch propagation, power dissipation can be an issue. Larger the combinational path leading to a node, larger the number of probable toggles possible; greater is the expected power dissipation.

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