2-input AND gate using 2:1 mux

2-input AND gate implementation using 2:1 mux: Figure 1 below shows the truth table of a 2-input AND gate. If we observe carefully, OUT equals '0' when A is '0'. And OUT follows B when A is '1'. So, if we connect A to the select pin of a 2:1 mux, AND gate will be implemented if we connect D0 to '0' and D1 to 'B'.

Figure 1: Truth table of AND gate

Figure 2 below shows the implementation of 2-input AND gate using a 2:1 multiplexer.

Figure 2: Implementation of AND gate using a 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux

2-input NAND gate using 2:1 mux: Figure 3 below shows the truth table of a 2-input NAND gate. If we observe carefully, OUT equals '1' when A is '0'. Similarly, when A is '1', OUT is B'. So, if we connect SEL pin of mux to A, D0 pin of mux to '1' and D1 to B', then it will act as a NAND gate.

Figure 3: Truth table of 2-input NAND gate

Figure 4 below shows the implementation of a 2-input NAND gate using 2:1 mux.

Figure 4: Implementation of 2-input NAND gate using 2:1 mux

Also read:

• NOT gate using 2:1 mux
• 2-input XOR gate using 2:1 mux
• 2-input NOR gate using 2:1 mux
• 2-input XNOR gate using 2:1 mux
• 2-input OR gate using 2:1 mux
• 2-input AND gate using 2:1 mux