IIT Madras - Interview Experiences

Yes. After the failure of IISC Bangalore, I went to IIT Madras. I came here for Texas Sponsored MS.
It is one of the very good programs in IITs in the field of VLSI. IIT Madras is best for some one interested in Analog Research.  I was prepared for a tough fight. 

I knew mentally that It would be very difficult for me to clear the rounds because the number of people whom they will call is all ECE Rankers < 1000 and all Instrumentation and Electrical guys with Ranks< 750.

There is no reservation for this program. Luckily I haven't had any.

I got there on May 1stitself. I had a friend Charan working in TCS. Both of us roamed around the city and went to sea shore and few other places. It was as if I came there for some other reason. But thanks to him, atleast roamed a lot in Chennai. Thanks for him for a lovely care.

Next day on May 2nd , I went to the College – IIT Madras. In the presentation by the Texas team, they have really made us get goose bumps for the company it is. It produces diverse products and today Texas is in the top position in Analog research and IIT Madras is like heaven for analog research. 

It has 3 gods of Analog – Nagendra Krishnapura, Anirudhan, Shanti Pavan.  Texas came with an offer of employment of 16L after successful completion of MS, although nothing is assured. They will also give us higher stipend of 20K for the first year and 30K for the next 2 years.  

I went to the written test. I was shocked to see the questions. They were not easy but neither were they out of box. I can assure you u can never come across such questions any where in any question bank.


Most of the guys were in the same mood. Don't know what to comment. They were such questions which required us to be theoretically Mr. Perfect, nothing less.

I will update all the questions once I sit back to write all those in a notebook. In the mean while you can refer to the given link. Actually One thing is that Texas will only ask transient analysis and Analog Electronics to a very deep level.


But this was a bit too tougher on my part. I knew that syllabus is Network theory and Analog Electronics. But I could not clear the written round due to my lack of understanding things in even perfect way.

It required a lot of mastery of the subject much better than mine.


But learnt again that I still need to improve.

               With low levels of Confidence and may be in a spot of bother whether I will not be able to manage to get VLSI seat through Interview, I read more for the next time... 

                            Chalo Delhi. next


IISC - Interview Experiences

Hi Every one ..

So this is the post where in I will be sharing with all of you my CEDT written test experience.

Just like others, don't just have a negative opinion about IISC Bangalore that it has only research guys and no placements. It is very good institute and if you want to study peacefully, it is the best.

Be prepared for some good knowledge sharing during the two years of Mtech in IISC.

So the written test was scheduled on April 20th 2015, I arrived 1 day before. I have one friend there Satya Narayana who is studying there as CEDT student. He got 699 rank(OBC) last year ( When I got 751 Rank in General ).  Last year, I accompanied him to IISC because I had a call from Computation sciences with my last year rank. So due to this, It didn't take much of time for me to go to IISC after getting down at the Bus stop.

I will share few questions that I remember.

1. How to make mux with de mux and vice versa.

2. 5 to 8 questions on Embedded Systems ( Strange experience for most of the students )

3. Simple Biasing question on BJT Transistor

4. Simple question on Flip Flops and Micro Processor

5. Question on Sub Threshold Region in MOSFET

6.  Easy 2 questions in Mathematics

7.  EM Theory about trasmission

8. Design from 15V to 5V un regulated power supply

9.  1 question on IPV4 and IPV6. It had one question also about router working.

10. Little Endian and Big Endian question.

11. Rise Time and fall time question and graph of output voltage vrs time when you have a capacitor and resistor connected in the output stage of a transistor

12. Design a circuit for Chess board type of K-Map. Find the minimum number of xnor and xor gates.

I will keep on updating few other questions.. as and when I remember them or get it from few of my friends.... But mostly I have done it.

Some how after the Exam, I felt I would be in with 60% chance and 40% out.
     
               Unfortunately - the 40% came true.....


So immediately took a train to Hyderabad and came back...

                     Next Journey is to the Ultimate Madras after 1 week gap...

                                                                                      Check it out next. .