Data checks : data setup and data hold in VLSI

Many a times, two or more signals at analog-digital interface or at the chip interface have some timing requirement with respect to each other. These requirements are generally in the form of minimum skew and maximum skew. Data checks come to rescue in such situations. Theoretically speaking, data-to-data checks are applied between two arbitrary data signals, none of which is a clock. One of these is called constrained pin, which is like data pin of the flop. The other is called related pin, which is like clock pin of the flop. In the figure below, is shown two data signal at a boundary (possibly analog hard macro) having some minimum skew requirement between them.

Figure 1 : Two signals arriving at a boundary having skew requirement

Data-to-data checks are zero cycle checks: An important difference between normal setup check (between a clock signal and a data signal) and data-to-data checks is that data-to-data checks are zero cycle checks while normal setup  check is single cycle check. When we say that data checks are zero-cycle checks, we mean that these are between two data signals that have launched at the same clock edge with respect to each other.

As shown in the figure (i) below, traditional setup check is between a data signal launched at one clock edge and a clock. Since, the data is launched at one clock edge and is checked with respect to one edge later, it is a single cycle check. On the other hand, as shown in figure (ii), data-to-data check is between two signals both of which are launched on the same clock edge. Hence, we can say  data-to-data checks are zero cycle checks.

 

Figure 2 : (i) Normal setup check between a data signal and a clock signal, (ii) Data to dat setup check between two data signals

What command in EDA tools is used to model data-to-data checks: Data checks are modeled in EDA tools using ‘set_data_check’ command.

                Set_data_check –from A –to B –setup <x>

                Set_data_check –from A –to B –hold <y>

Here, A is the related pin and B is the constrained pin. The first command constrains B to toggle at least ‘x’ time before ‘A’. Second command constrains ‘B’ to toggle at least ‘y’ time after ‘A’.

Data setup time and data hold time: Similar to setup time and hold time, we can define data setup time and data hold time as follows:

• Definition of data setup time: Data setup time can be defined as the minimum time before the toggling of reference signal for which constrained signal should become stable. In the example above, <x> is data setup time.
• Definition of data hold time: Data hold time can be defined as the minimum time after the toggling of reference signal for which constrained signal should remain stable. In the example above, <y> is data hold time.

Modeling data-to-data checks through liberty file: We can model data checks through .lib also. There are constructs that can be used to model data-to-data checks. These are non_seq_setup_rising, non_seq_setup_falling, non_seq_hold_rising and non_seq_hold_falling. These commands specify setup and hold data-to-data checks with respect to rising or falling edge of reference signal respectively. E.g. ‘non_seq_setup_falling’ represents data setup check with respect to falling edge of reference signal. ‘rise_constraint’ and ‘fall_constraint’ can be used inside these to model the setup and hold checks for rising and falling edge of constrained signal. Figure 3 below shows an example of modeling data setup check through liberty file.

Figure 3 : Modeling data-to-data checks through .lib using non_seq_setup_rising

In which cases data-to-data checks are applied: Data checks are normally applied where there is a specific requirement of skew (either minimum of maximum) or race condition (where the order of arrival of two signals can affect output and the intention is to get one of the probable outputs by constraining one signal to come before the other) between two or more signals. These may be required where:

• At the digital-analog interface within a chip where analog signals at the analog block boundary are required in a specific order

• At the chip boundary, some asynchronous interface signals may have skew requirements

How data checks are useful: As we have seen above, data checks provide a convenient measure to constrain two or more data signals with respect to each other. Had these checks not been there, it would have been a manual effort to check the skew between the two arriving signals and to maintain it. Also, it would not have been possible to get the optimization done through implementation tool as these would not have been constrained for it.

References:

1.  How to constrain the data skew check in the .lib ? - http://tech.tdzire.com/how-to-constrain-the-data-skew-check-in-the-lib/ 
2. Static timing analysis for nanometer designs – a practical approach by J Bhasker and Rakesh Chadha

Also read:

• Setup time and hold time - static timing analysis
• False paths - what are they
• Propagation delay
• What is static timing analysis

Clock latency

Definition of clock latency (clock insertion delay): In sequential designs, each timing path is triggered by a clock signal that originates from a source. The flops being triggered by the clock signal are known as sinks for the clock. In general, clock latency (or clock insertion delay) is defined as the amount of time taken by the clock signal in traveling from its source to the sinks. Clock latency comprises of two components - clock source latency and clock network latency.

• Source latency of clock (Source insertion delay): Source latency is defined as the time taken by the clock signal in traversing from clock source (may be PLL, oscillator or some other source) to the clock definition point. It is also known as source insertion delay. It can be used to model off-chip clock latency when clock source is not part of the chip itself. 

• Network latency of clock (Network insertion delay): Network latency is defined as the time taken by the clock signal in traversing from clock definition point to the sinks of the clock. Thus, each sink of the clock has a different network latency. If we talk about the clock, it will have:
• Maximum network latency: Maximum of all the network latencies
• Minimum network latency: Minimum of all the network latencies
• Average network latency: Average of all the network latencies

Total clock latency is given as the sum of source latency and network latency. In other words, total clock latency at a point is given as follows:

       Clock latency = Source latency + Network latency

It is generally stated that for a robust clock tree, ‘sum of source latency and network latency for all sinks of a clock should be equal’. If that is the case, the clock tree is said to be balanced as this means that all the registers are getting clock at the same time; i.e., clock skew is zero.

Figure 1 : Figure showing source latency and network latency components of clock latency

Figure 1 above shows the two components of clock latency, i.e. source latency and network latency. Each flop (sink, in general) has its own latency since the path traced by clock from source to it may be different. The above case may be found in block level constraints in case of hierarchical designs wherein clock source is sitting outside the block and clock signal enters the block through a block port. It may also represent a case of a chip in which the clock source is sitting outside; e.g. some external device is controlling the chip. In that case, clock source will be sitting inside that device.

How to specify clock latency: In EDA tools, we can model clock latency using SDC command ‘set_clock_latency’ to imitate the behavior there will be after clock tree will be built. Using this command, we can specify both the source latency for a clock as well as the network latency. After clock tree has been built, the latency for the sinks is calculated by the tool itself from the delays of various elements. However, in case the clock source is sitting outside, it still needs to be modeled by source latency even after the clock tree synthesis. To specify clock latency for clock signal named ‘CLK’, we may use SDC command set_clock_latency:

                set_clock_latency <value> CLK

                set_clock_latency <value> CLK –source

First command will specify the network latency whereas the second command will specify the source latency for CLK.

Also read:

• Clock - the incharge of synchronous designs
• Timing corners - dimensions in timing signoff
• Ensuring glitch-free propagation of clock
• Clock switching and clock gating checks
• Can hold be frequency dependent

Hope you liked this post. Let us know of your views through comments.