As we know, scan chains involve shifting the data through scan flops starting from tester through scan_in port, going through every scan flop in the chain and finally going to tester through scan_out port.
Now, a clock gating check, in principle, is a signal coming in the path of clock propagation and dynamically switching on/off the clock pulse at the output of the gate. Clock gating check can be visible in static timing analysis because of mode merging or any other reason. And if not valid, can be dispositioned accordingly through "set_disable_clock_gating_check" command. However, care must be taken to understand all architectural use-cases before disabling the particular clock gating check. In the context of shift mode, let us assume that a clock gating check is being formed. There can be two possible cases:
1. The output of the gate is not going to clock pin of a scan flop: In this case, it is not a valid shift clock gating check. There can be two possible sub-cases:
a. It is fanning out to a non-clock pin: In this case, since not going to a valid clock sink, can be ignored right away. However, we must examine properly that the fanout pins dont involve any liberty related issue such as clock attribute missing in lib etc.
b. The clock pins in fanout are all non-scan flops: In this case, if the mode in question is pure shift mode and none of the logic on chip is expected to operate functionally, we can consider it to be an invalid clock gating check. However, as said earlier, extreme care must be taken to arrive at this conclusion.
2. The output of the gate goes to clock pin of a scan flop: In this case, if the enable toggles, it will dynamically turn the clock on and off for the scan flop in fanout. As an example, lets assume a scan flop output goes to ICG enable pin. In this case, ignoring SE pin functionality for now, it may make the output of ICG to go 0 for a few clock cycles. During this duration, since the fanout flop(s) dont receive clock, scan chains will have redundant data or loss of data through shifting. Due to this, there will be loss of efficiency in scan shifting, which may be quite costly. Due to this reason, the shift clock path should be without any gating. If any such thing is seen, it would be either a design bug or a missing set_case_analysis. For instance, the example in question has missing set_case_analysis at ICG/SE pin (see link).
Thus, the conclusion of this post is that in principle, scan paths dont have any clock gating checks and we can disable all clock gating checks. However, we must adhere to extreme caution to not miss any corner case scenario as discussed above.