VLSI UNIVERSE

What is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path...

There can be 4 cases of latch-to-flop timing paths as discussed below: 1. Positive level-sensitive latch to positive edge-triggered regi...

Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?...

In this realistic world, nothing is ideal. A signal travelling along a wire/cable/transmission line is susceptible to noise from the sur...

As we discussed in ‘’ Is it possible for a logic gate to have negative propagation delay ”, a logic cell can have negative propagation de...

We often encounter people argue that hold check is frequency independent. However, it is only partially true. This condition is true onl...

Definition of multicycle paths : By definition, a multi-cycle path is one in which data launched from one flop is allowed (through archi...

In the post ( Setup time and hold time – static timing analysis ), we introduced setup and hold timing requirements and also discussed why...