VLSI UNIVERSE
Why clock gating checks not there in shift mode
›
As we know, scan chains involve shifting the data through scan flops starting from tester through scan_in port, going through every scan fl...
Why there needs to be a lockup latch inserted because of DFT architecture reasons
›
In the post lockup latches , we mentioned that it may not be advisable/allowed to have a positive edge triggered flop flop followed by a neg...
Why NMOS leads to a strong 0 and a weak 1
›
We frequently hear that an NMOS can pass a strong "0" and only a weak "1". Similarly, a PMOS can only pass a weak "...
5 comments:
Does inserting lockup latch affect Logic Equivalence Check (LEC)
›
Logic equivalence check is normally carried out to ensure some processing of the design (example logic synthesis) has not resulted in chang...
3 comments:
Analogy between English and C as a language
›
In our first post, we discussed that any programming language is a language in the first place. So it must be analogous to a language in how...
›
Home
View web version
