Showing posts with label Static timing analysis. Show all posts
Showing posts with label Static timing analysis. Show all posts

Interview questions related to clock jitter and duty cycle variations

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Below we list few of our posts related to clock jitter and duty cycle variation. Happy learning. Clock jitter : Disusses the definition...
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Intricacies in handling of half cycle timing paths

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What is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path...
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Is hold always checked on the same edge?

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One of the guys asked me a question, "Why is hold always checked on the same edge?" Normally, it is taught in books/colleges tha...
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What is the difference between a normal buffer and clock buffer?

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A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a re...
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How to fix min pulse width violation

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In our previous posts, we discussed about the duty cycle, duty cycle variation and duty cycle degradation. Bad duty cycle impacts half cyc...
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Duty cycle degradation

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In the post, we discussed about duty cycle variation of the clock source. However, this is not the only pain in half cycle timing paths. A...

Duty cycle variation of inter-clock timing paths

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In the post, duty cycle variation, we understood what duty cycle variation is, and how to apply for intra-clock timing paths. But of simila...
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Duty cycle variation

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Duty cycle variation : Similar to jitter in clock period, there can be variations in duty cycle of the clock source due to uncertainty in ...
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Duty cycle of clock

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Duty cycle : Duty cycle of a clock is defined as the fraction of a period of clock during which the clock is in active state. Duty cycle o...
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Which type of jitter matters for timing slack calculation?

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In the post Clock jitter , we learnt about the basics of clock jitter. We also learned about different types of clock jitter. Now, the ques...
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Clock jitter

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Clock jitter : By definition, clock jitter is the deviation of a clock edge from its ideal position in time. Simply speaking, it is the ina...
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Clock skew

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Clock skew is one of the most important parameters of a good physical design implementation. Keeping the clock skew to a minimum is consi...
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Divide by 2 clock in VHDL

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Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequen...
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Minimum pulse width

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All the sequential elements need some minimum pulse (either high or low) to ensure that the data has been captured correctly. In other wor...

Setup checks and hold checks for latch-to-flop timing paths

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There can be 4 cases of latch-to-flop timing paths as discussed below: 1. Positive level-sensitive latch to positive edge-triggered regi...
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