In the post, duty cycle variation, we understood what duty cycle variation is, and how to apply for intra-clock timing paths. But of similar importance is duty cycle variation as applied to inter-clock timing paths. Let us discuss these cases one-by-one:
Root clock to root-inverted clock: Inverted clock is same as root clock in frequency, with phase inverted. So, duty cycle variation needs to be applied for following cases:
Root clock to odd 50% divided clock: In this scenario, we need to apply extra uncertainty for the following cases:
Root clock to even 50% divided clock: In this case, we need to apply duty cycle uncertainty for the following cases:
So, the rule of thumb is same. Wherever there is a timing path wherein both rising and falling edges of root clock are involved, duty cycle variation will come into play. If you just keep this basic thing into mind, duty cycle variation will never haunt you. :-)
Root clock to root-inverted clock: Inverted clock is same as root clock in frequency, with phase inverted. So, duty cycle variation needs to be applied for following cases:
- Root rise edge -> generated rise edge
- Root fall edge -> generated fall edge
- Generated rise edge -> Root rise edge
- Generated fall edge -> Root fall edge
Following commands will be needed to be applied:
set_clock_uncertainty -rise_from root_clk -rise_to gen_clk <duty_cycle>
set_clock_uncertainty -fall_from root_clk -fall_to gen_clk <duty_cycle>
set_clock_uncertainty -rise_from gen_clk -rise_to root_clk <duty_cycle>
set_clock_uncertainty -fall_from gen_clk -fall_to root_clk <duty_cycle>
Root clock to odd 50% divided clock: In this scenario, we need to apply extra uncertainty for the following cases:
- Root rise edge -> Generated fall edge
- Root fall edge -> Generated rise edge
- Generated rise edge -> Root fall edge
- Generated fall edge -> Root rise edge
Following commands will need to be applied for this case:
set_clock_uncertainty -rise_from root_clk -fall_to gen_clk <duty cycle>
set_clock_uncertainty -fall_from root_clk -rise_to gen_clk <duty cycle>
set_clock_uncertainty -rise_from gen_clk -fall_to root_clk <duty cycle>
set_clock_uncertainty -fall_from gen_clk -rise_to root_clk <duty cycle>
Root clock to even 50% divided clock: In this case, we need to apply duty cycle uncertainty for the following cases:
- Root fall edge -> Generated rise edge
- Root fall edge -> Generated fall edge
- Generated rise edge -> Root fall edge
- Generated fall edge -> Root fall edge
Below figure shows these cases for a 50% divided clock from root clock.
So, the rule of thumb is same. Wherever there is a timing path wherein both rising and falling edges of root clock are involved, duty cycle variation will come into play. If you just keep this basic thing into mind, duty cycle variation will never haunt you. :-)
Also read:
Hello, I read the intra clock and inter clock duty cycle variation topics.
ReplyDeleteI've understood why for "Duty cycle variation of even 50% divided clock" the duty cycle variation is not applied, it is because both positive and negative edges if divided clock are aligned with positive edge of master clock.
But in case "interclock" duty cycle variation for the case "Root clock to even 50% divided clock", the positive and negative edge of divided clock aligns with positive edge of root clock, then why is duty cycle variation applied in this case?
You said everything right, positive and negative edges of divided clock align with positive edge of root clock.
DeleteBut negative edge of root clock does not align with any edge of divided clock, so any path between negative edge of root clock and any edge of divided clock should have duty cycle variation being considered as a margin.
In the last example, both positive and negative edge of generated clock align with positive edge of root clock. As per article " duty cycle variation" there should not be any duty cycle variation applied here. how is inter-clock v/s intra-clock spec playing a role here ?
ReplyDeleteHi
DeleteYou are partially right, there can be following cases:
1. No intra-clock duty cycle variation for generated clock, since only positive edges of root clock are referenced.
2. No inter-clock duty cycle variation from/to positive edge of root clock to/from generated clock.
3. But cases where negative edge of root clock is involved, we need to take into account duty cycle variation.
I hope I was able to answer your query.