VLSI UNIVERSE

LVS stands for Layout vs Schematic. It is one of the steps of physical verification; the other one being DRC (Design Rule Check). While DR...

Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?...

As we discussed in ‘’ Is it possible for a logic gate to have negative propagation delay ”, a logic cell can have negative propagation de...

Static timing analysis of a design is performed to estimate its working frequency after the design has been fabricated. Nominal delays of ...

Definition of multicycle paths : By definition, a multi-cycle path is one in which data launched from one flop is allowed (through archi...

In the post ( Setup time and hold time – static timing analysis ), we introduced setup and hold timing requirements and also discussed why...