VLSI UNIVERSE
Clock gating checks in case of mux select transition when both clocks are running
›
PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. W...
16 comments:
Intricacies in handling of half cycle timing paths
›
What is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path...
2 comments:
‹
›
Home
View web version
