VLSI UNIVERSE

Showing posts with label timing. Show all posts
Showing posts with label timing. Show all posts

Interesting problem – Latches in series

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Problem: 100 latches (either all positive or all negative) are placed in series (figure 1). How many cycles of latency will it introduce?...
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Noise margins

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In this realistic world, nothing is ideal. A signal travelling along a wire/cable/transmission line is susceptible to noise from the sur...

Lockup latch – principle, application and timing

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What are lock-up latches : Lock-up latch is an important element in scan-based designs, especially for hold timing closure of shift modes....
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