VLSI UNIVERSE
Showing posts with label
latch principle
.
Show all posts
Showing posts with label
latch principle
.
Show all posts
Basics of latch timing
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A latch is a digital logic circuit that can sample a 1-bit digital value and hold it depending upon the state of an enable signal. Based u...
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Setup checks and hold checks for latch-to-flop timing paths
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There can be 4 cases of latch-to-flop timing paths as discussed below: 1. Positive level-sensitive latch to positive edge-triggered regi...
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