VLSI UNIVERSE
Showing posts with label
finite state machine
.
Show all posts
Showing posts with label
finite state machine
.
Show all posts
Why setup is checked on next edge and hold on same edge? Setup and hold – the state machines essentials
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Hi friends, in the post State machines – a practical perspective , we learnt about state machines. We also discussed different aspects of ...
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Divide by 2 clock in VHDL
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Clock dividers are ubiquitous circuits used in every digital design. A divide-by-N divider produces a clock that is N times lesser frequen...
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Delay line based Time to digital converter
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A time to digital converter is a circuit that digitizes time; i.e., it converts time into digital number. In other words, a time-to-digita...
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