Showing posts with label clock gating. Show all posts
Showing posts with label clock gating. Show all posts

How clock gating reduces power dissipation

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As discussed in clock gating - basics , enable signal coming in data path is transferred into clock path in order to save dynamic power. B...
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Clock gating checks in case of mux select transition when both clocks are running

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PROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. W...
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Design problem: Clock gating for a shift register

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Problem : There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportun...

Clock gating - basics

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The dynamic power associated with any circuit is related to the amount of switching activity and the total capacitive load. In digital VLS...
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Clock gating cell

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Clock gating is a very common technique to save power by stopping the clock to a module when the module is not operating. As discussed in ...
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Quiz : Clock gating check at a complex gate

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Problem: Consider a complex gate with internal structure as shown in figure below. One of the inputs gets clock while all others get data ...

Clock gating checks

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Today’s designs have many functional as well as test modes. A number of clocks propagate to different parts of design in different modes. ...
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